搜索资源列表
ref-ddr-sdram-verilog.zip
- sdram的verilog的源码实现,sdram verilog source code realizes
CODE.rar
- AHB总线下的slave ram的verilog代码,AHB bus slave ram verilog
FPGA-RAM-Verilog
- 用Verilog语言编写的FPGA，对波形数据用RAM存储-Using Verilog language FPGA, using the waveform data stored in RAM
ug_ram
- RAM design for FPGA in verilog
ram_Test
- RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram
ram2
- RAm的 verilog描述，在Quartus中验证正确，可根据程序改成其他参数-Verilog descr iption of RAm in Quartus verify correct procedures can be changed in accordance with other parameters
RAM
- 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
ram_of_Fusion
- Fusion中的双口RAM编写，可以实现双向的调用。用Verilog编写。-Fusion in the preparation of dual-port RAM, you can realize a two-way call. Prepared using Verilog.
RAM
- 用VerilogHDL写的ram程序，对初学者会有帮助。-Writing the ram with VerilogHDL procedures will be helpful for beginners.
c51
- 51单片机，USB，触摸，TFT,的等综合应用，高级别。（usb+flash+touch+tft+ram综合测试）-51 single-chip, USB, Touch, TFT, integrated applications (usb+ flash+ touch+ tft+ ram General Test)
RAM_Examples
- Verilog hdl code for representing ram and rom "memory" using many methods
spmem.tar
- Sinlge port RAM VHDL/Verilog design
dual_RAM
- vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
x3cs400_uart
- 基于X3cS400的串口通讯程序，开发环境ISE7.0，使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA， develop enviroment： ISE7.0，completed by verilog。 The result could be seen on the Uart debug assitant.
RAM
- Ram with 8 bits implemented in vhdl verilog code
RAM
- 单端口RAM，自己写的单端口RAM，同步写入同步读出，包括TESTBENCH和测试模拟文件-RAM
ram
- verilog 编写的ram代码，开发环境为quartus-ram write verilog code development environment for quartus
ram
- 用verilog实现32字节8位RAM（触发器和M4K），用LPM实现RAM-32-byte by 8-bit verilog RAM (triggers and M4K), achieved by LPM RAM
一种arm7源码（Verilog）
- 一种arm7源码（verilog），arm7结构比较老了，不过用来初学还是不错的(A kind of ARM7 source code (Verilog))