搜索资源列表
DPRamComm
- 基于双口RAM的单片机间通信 从书上摘抄的，仅供参考-Based on the single-chip dual-port RAM communication excerpt from the book, and for reference only
DPRam_Comm
- 基于双口RAM的单片机间通信 从书上摘抄的，仅供参考-Based on the single-chip dual-port RAM communication excerpt from the book, and for reference only
25
- 基于双口RAM的单片机间通信-Based on the single-chip dual-port RAM communication
bram_delay
- Verilog编写的代码，单口RAM用程序控制地址，而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file
memory_cores
- 通用ram源码包，包括双口ram，单口ram，fifo等-general ram source package，include dual port ram，single port ram，fifo，etc.
ex9_cof_M4K_test1
- 这是一个基于M4K块得单口RAM配置仿真实验程序-This is an M4K block was based on a single-port RAM configuration simulation program
Single-port-RAM-
- 单口RAM带CLR信号的verilog程序。很详细的.-Single-port RAM with a CLR signal
ram
- ram single-port RAM in write-first mode.
vhdl
- single-port RAM in write-first mode. module raminfr (clk, we, en, addr, di, do) input clk input we input en input [4:0] addr input [3:0] di output [3:0] do reg [3:0] RAM [31:0] reg [4:0] read_addr always @(po
ram_sp_ar_sw.v
- this is a verilog source code for Single Port RAM Synchronous Read/Write.
ram_sp_sr_sw.v
- this is a verilog source code for Single Port RAM Synchronous Read/Write.
spram
- 基于altera fpga 的单口ram ip核的应用实例，包含整个工程和moselsim仿真，数据，写使能，地址都是用模块来产生的。-Altera fpga single port ram the ip core application instance, contains the entire engineering and moselsim of simulation data, Write Enable, addresses are generated by the module.
RAM
- 基于verilog的双口和单口RAM的实现-Verilog dual port and single port RAM-based implementation
RAM
- altera FPGA上的RAM源码 单端口结构 -the RAM the source single port structure altera FPGA
single_port_ram_with_init
- Single-port RAM with single read/write address and initial contents
single_port_ram
- Single port RAM with single read/write addre-Single port RAM with single read/write address
DistRAM
- Distributed Single Port RAM
single_port_ram
- Single port RAM file VHDL source code
Dual-port-RAM-data-acquisition
- 利用传统方法设计的高速数据采集系统由于集成度低、电路复杂，高速运行电路干扰大，电路可靠性低，难以满足高速数据采集工作的要求。应用FPGA可以把数据采集电路中的数据缓存、控制时序逻辑、地址译码、总线接口等电路全部集成进一片芯片中，高集成性增强了系统的稳定性，为高速数据采集提供了理想的解决方案。-Using traditional methods of high-speed data acquisition system design due to low integration, circuit
spram
- vhdl code of single port ram