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verilog1
- The Universal Asynchronous Receiver Transmitter (UART) is a popular and widely-used device for data communication in the field of telecommunication. There are different versions of UARTs in the industry.
x2uart-all
- 适用异步收发器设计的vhdl语言,是学习UART知识的好例程-Asynchronous Receiver Transmitter apply VHDL design language, are a good knowledge of study UART routines
SC28L198
- SC28L198是一个带有8个全双工异步通道UART的芯片，每个UART通道的接收器和发送器都拥有16字节深度的FIFO。芯片的每个UART通道除了基本的异步通信功能外，还可实现软件流控制（in-band flow control）、硬件流控制（out-of-band flow control）、以及多点模式（唤醒模式或RS-485模式）等，同时每个UART都有4个外扩的I/O引脚，每个外扩I/O引脚都为功能复用。 本资料包含完整测试程序，应用文档，电路原理图及PPT演示文档等。-SC28L
uart_tx
- Interface for Transmitter UART
UARTyulanyajiekoulianjie
- UART(通用异步收发器)与蓝牙的接口连接,解释的非常详细,欢迎下载交流.-UART (Universal Asynchronous Receiver Transmitter) and Bluetooth interface, a very detailed explanation, please download the exchange.
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a
SoC-verify-and-debug
- 摘要：介绍SoC(片上系统)软硬件协同验证中的软件仿真，给出验证uART(通用异步收发器)硬件接口的应用程序范例。利用GNU工具链开发SoC软硬件协同验证中的应用程序，并利用仿真器进行软件仿真，仿真结果正确。可以根据处理器的类型对GNU工具链进行配置，使开发流程适合所有GNu支持的处理器，方法具有一般性。根据开发者的具体需要，开发soc芯片的应用程序用于软硬件协同验证。-Abstract: SoC (system on chip) hardware and software co-verific
uart_tx_test
- 基于verilog的串口uart发送端实现-Verilog-based serial transmitter to achieve
test
- A universal asynchronous receiver/transmitter, abbreviated UART ( /ˈ juː ɑrt/), is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in
UART
- 基于FPGA的（Universal Asynchronous Receiver Transmitter，UART）串行通信设计论文-FPGA BASIC FOR （Universal Asynchronous Receiver Transmitter，UART）
soft-uart.tar
- The transmitter part of a RS232 uart, pure software, no hardware support needed. Code can transmit up to 230400 baud on an attiny25/45/85 with an 18.342MHz crystal
uart
- Verilog 编写全双工UART input clk, // 这个模块的主时钟 input rst, // 同步复位信号 input rx, // 串口接收端口 output tx, // 串口发射端口 input transmit, // 发送信号 input [7:0] tx_byte, // 发送的字节 output received, // 表明，已接受到一个字节 output [7:0] rx_
uart_tx_and_rx
- A verilog code for UART transmitter and receiver system-A verilog code for UART transmitter and receiver system...
UART
- 本论文使用Verilog HDL 语言描述硬件功能，利用QuartusII 5.0在 FPGA 芯片上的综合描述,采用模块化设计方法设计UART（通用异步收发器）的各个模块。-The paper using Verilog HDL language to describe hardware features, the use of the FPGA chip QuartusII 5.0 comprehensive descr iption of the modular design approa
uart_tx
- uart transmitter module in verilog hdl
UART
- UART Package Declaration with Receiver Transmitter !
uart_mm
- Its uart transmitter and receiver
xapp223
- UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buffer for Virtex, Virtex-E and Spartan-II FPGAs-UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buf
PC机 采用主从方式 采集总线上的多块MINI板
- 主从方式，主机通过CAN读取从机的单片机温度数据，主机收到的数据在PC端串口助手显示。 单片机stm32f103c8t6(Master/Slave Master read temper data from Slave through Can-bus. The temperature data Master received will print to PC through UART&USB transmitter. MCU is stm32f103c8t6.)
uart_test
- 收发端都采用2M波特率发送串口数据，通过PIN口直接输入输出串口数据，目的是为了跟外围高速器件完成高速的串口数据的收发，普通USB转串口的都只能支持不到1M的波特率，内部采用乒乓FIFO进行时钟域切换以及缓存(The transmitter and receiver are used 2M baud rate serial data transmission, directly through the PIN port serial input and output data, the purp