搜索资源列表
FPGA
- 用verilog实现的串口收发数据程序，已经调试通过
串口通信收发模块
- verilog编写的串口通信的接收模块和发送模块，经过仿真有效
FPGA-URAT.rar
- FPGA与PC串口自动收发程序,verilog源程序,FPGA and the PC serial port automatically sending and receiving process, verilog source code
my_232
- verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
series_port
- 用verilog语言编写的串口收发程序，可以进行429总线数据与rs232口的通信。-With verilog program written in serial transceivers, can be 429 bus data and rs232 mouth communication.
hdl
- ACTEL串口收发 Verilog语言描述-ACTEL serial port transceiver
sim_uart
- uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no par
rt
- 用Verilog编写的串口收发程序，通过参数调整，就可以设定/更改波特率，收发数据长度，已调试。-Serial transceivers with Verilog program, prepared by adjusting parameters, you can set/change the baud rate, send and receive data length, is debugging.
uartverilog
- 用verilog语言编写uart程序。模拟串口时序进行收发数据操作。-verilog uart
FPGA_UART
- 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA
Verilog-uart
- Verilog状态机实现的串口串口收发模块 -Verilog state machine for uart
uartverilog
- 该程序是Verilog写的串口收发程序，具有基本的收发功能，经过验证，能使初学者很好了解rs232，和Verilog-The program is written in Verilog serial transceiver program, with the basic send and receive functions, proven, good for beginners can understand rs232, and Verilog
uart_verilog
- 一个VERILOG串口收发的例子，可以收发单字节，适当加小量代码就可实现任意字节的接收。-VERILOG a serial port to receive example, can receive a single byte, appropriate to add a small amount of code can be any byte receive.
verilog串口收发模块程序
- 基于verilogHDL语言的RS232串口收发模块程序
verilog串口通信程序
- 串口通信程序，用于fpga的串口收发，并讲解了串口通信原理。(Serial communication program is used to receive and transmit the serial port of FPGA, and the principle of serial communication is explained.)
uart
- 用verilog实现UART串口收发。状态机形式实现，波特率可调(Use verilog to achieve UART serial transceiver. State machine form, adjustable baud rate)
uart
- 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)
uart
- 实现串口的收发，可以稳定的运行，经过测试，可以完全应用于项目中。(The implementation of the serial port and transceiver, can run stable)
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Ve