搜索资源列表
ref-ddr-sdram-verilog.zip
- sdram的verilog的源码实现,sdram verilog source code realizes
(fpga)sdram.rar
- verilog 代码，读写SDRAM 不带仿真，需要自己编写测试文件,Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation
SDRAM.rar
- 瑞芯科技EFX400SL开发板上使用ISE创建的SDRAM控制器的工程源码,Rockchip EFX400SL technology development board created by the use of ISE projects SDRAM controller source
vga_core(vhdl).rar
- vga视频输出（vhdl），主要是从sdram中产生图形，输出到vga中,vga video outputs [vhdl], mainly arising from the SDRAM graphics, output to vga Medium
mem_ctrl_latest.tar
- 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
sdram-source
- SDR SDRAM 控制器的源代码 altera公司的-source code from altera
DDR_SDRAM
- ddr sdram 的控制程序，lattice的，比较好用的，大家-ddr sdram control program, lattice, and relatively easy to use, and we look
Sdram_Control_4Port
- DE2开发板提供的四端口SDRAM驱动，用户不需要对SDRAM直接操作，把SDRAM对用户透明化-DE2 development board provides four-port SDRAM drive, users do not need to direct the operation of the SDRAM, the SDRAM transparent to users
sdramvhdl
- SDRAM存储器芯片，FPGA的接口控制，VHDL语言编写-SDRAM memory chips, FPGA interface control, VHDL language
sdram_vhd_134
- Xilinx Sdram控制器VHDL源代码-Sound code of Xilinx Sdram Controller based on VHDL
ref-sdr-sdram-verilog
- SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
DDR_SDRAM_controller
- ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
ref-sdr-sdram-verilog
- 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
SDRAM_simulation_model
- sdram的测试程序 和读写程序 vhdl语言编写的-SDRAM testing procedures and to read and write procedures VHDL language
ref-ddr-sdram-vhdl
- 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
ref-sdr-sdram-vhdl
- 基于VHDL编写的SDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller
sdram_hr_hw
- 在FPGA硬件上实现计算机通过串口发数据给FPGA，数据保存到SDRAM中，然后又返回给计算机串口。-In FPGA hardware realize computer data through the serial port issued to FPGA, the data saved to SDRAM, and then again back to the computer serial port.
sdram
- artera 的一个SDRAM 模型（verilog）-artera an SDRAM model [verilog]
AlteraSDR-SDRAM
- Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
sdram
- 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。 先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程 目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是仿真模型 \rtl文件夹里面是源文件 \sim文