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signal_cpu_sort
- Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_ME
Digital-Design-and-Computer-Architecture-verilog.r
- 《数字设计和计算机体系结构》一书MIPS verilog源码。
mips_verilog.rar
- verilog语言实现的基于MIPS体系结构的微处理器程序，一个时钟周期执行一条指令。,verilog language MIPS-based microprocessor architecture, an implementation of a clock cycle instructions.
MIPS
- 带分支预测的MIPS流水线的verilog原代码。 详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
mips_multi
- mips processor multicycle non-pipelined microprocessor by verilog
mips2
- fully working mips pipelined with all files
SCMIPS
- 使用verilog代码描述了一种简单的单周期MIPS处理器实现，并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
Verilog-Source
- mips 处理器verilog文件， 适合做处理器开发的人员参考-the mips processor verilog file suitable processor development reference
PipelineCPU
- 这是我们设计的一个MIPS流水线CPU，基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于，5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型，这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句，从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU
MIPSCPU
- 这是verilog实现的MIPS多周期CPU在modelsim下面仿真通过-This is achieved verilog CPU MIPS multi-cycle simulation in modelsim below by