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pic16c57code
- 此代码可用modelsim进行仿真，修改rom之后可用quartusII进行综合，希望你们能对此程序不断完善。-modelsim this code can be used for simulation, After amending rom available quartusII comprehensive and hope that you can constantly improve this procedure.
cpu
- 16位的5级流水线cpu 采用vhdl代码 modelsim编译仿真-5-stage pipeline 16-bit cpu compiled simulation using modelsim vhdl code
how-to-make-a-testbench
- 怎样写一个testbench 讲述了怎样在ise或者modelsim里面怎样写仿真测试-How to write a testbench about how how to write a simulation test in ise modelsim inside
CPU_test
- 设计并通过modelsim仿真软件实现了一个可以在FPGA平台上运行的8位RISC的CPU软核-Design an 8-bit RISC CPU soft core on an FPGA platform and simulate it using ModelSim
MIPSCPU
- 这是verilog实现的MIPS多周期CPU在modelsim下面仿真通过-This is achieved verilog CPU MIPS multi-cycle simulation in modelsim below by
cui_mcu
- 微处理器设计（verilog）带测试验证代码modelsim仿真无误 -Microprocessor design (verilog) with modelsim simulation test verification code is correct
booth-multiplier
- 布斯乘法器设计源码。。功能完善，modelsim仿真通过-Booth Multiplier source. . Perfect function, modelsim simulation through