搜索资源列表
signal_cpu_sort
- Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_ME
embedded_risc
- 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
ARMCORE
- 用verilog语言实现的ARM7处理器的标准内核的源代码程序,nnARM, 具有很好的参考价值-using Verilog language of the standard ARM7 processor core source code procedures nnARM, who have a good reference value
sarm9beta
- arm9 架构简单core实现，可以综合，有实现步骤和说明，verilog代码编写。-arm9 core framework to achieve a simple, comprehensive, implementation steps and notes verilog code prepared.
8088verilog
- intel 8088 架构的verilog代码，可以综合下载，在fpga上实现8088调试。-intel 8088 verilog structure of the code can be integrated download, fpga achieved in 8088 debugging.
arm7_core_verilog
- arm7timi架构的verilog代码，可以仿真，通过学习，可以掌握arm7内部架构。-arm7timi verilog structure of the code can be simulated, through learning, be able arm7 internal structure.
risc_8051_v
- 流片过的risc_8051源代码 verilog语言描述的~-flow unit off risc_8051 verilog language source code described in the ~
ethernet_verilog
- 这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU），并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
ssp_arm.rar
- arm 的ssp—spi verilog源代码,arm of the ssp-spi verilog source code
usb11.tar
- USB1.1 SOURCE CODE verilog
arm7-verilog
- 用verilog写的仿ARM7的代码，在opencore上，现在被撤掉了-Written by verilog code like ARM7
MIPS
- 带分支预测的MIPS流水线的verilog原代码。 详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
Prefix_KoggeStone_32
- 经典的kogge-stone加法器结构，32结构，verilog代码-Classic kogge-stone adder structure, 32 structure, verilog code
TLC549
- FPGA控制TLC549 ，verilog代码-FPGA TLC549, verilog code
SCMIPS
- 使用verilog代码描述了一种简单的单周期MIPS处理器实现，并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
Verilog
- 一种面向并行Verilog模拟的代码分割器，好东西-Oriented parallel Verilog simulation code split, good thing
chengxing1
- 成型滤波器的verilog代码--Verilog source code for formatted wave filter. -Verilog source code for formatted wave filter
example15-I2C
- I2C协议，又称两线协议，该程序是板子上的I2C通信接口代码，用verilog风格的代码 -I2C protocol, also known as two-wire protocol, the program is on the board I2C communication interface code, verilog code style
fullAdder32
- 阵列加法器,实现加法功能，快速加法的功能，verilog代码-Array adder adding function to achieve rapid addition of features, verilog code
CPU-master
- 单周期CPU的Verilog源码实现，基于Vivado(Single cycle CPU Verilog source code implementation, based on Vivado)