搜索资源列表
mux21
- 二选一多路选择器的设计压缩包, 采用原理图方式和VHDL方式,quartusII 软件设计, 包含各种设计文件及目标下载文件.-mux21 design package, adopts the principle diagram method and VHDL, quartusII design software, download file contains all kinds of design documents and target.
DTGD16x16
- FPGA控制点阵LED16x16显示多个汉字，包括原理图设计以及详细的源程序设计，内容较为详细。-FPGA control LED16x16 dot matrix display multiple characters, including schematic design and detailed design of the source code, more detailed content.
FIR_OVER
- 基于FPGA的FIR滤波器的设计，包括每个模块的设计和顶层原理图。-FIR filter design based on FPGA, including the design and top-level schematic of each module.
ask
- 基于Quartus9开发的一个关于ASK调制和解调的仿真，顶层用原理图，各个模块使用VHDL语言编写-Quartus9 developed a simulation on ASK modulation and demodulation based on the top floor with a schematic, each module using VHDL language
GPS
- 本程序实现功能为接受GPS接收机时间信息，并编码形成IRIG-B时间码，同时跟设备总线通过485进行通信。包括原理图，单片机程序及CPLD程序。-This program implements functionality GPS receiver for receiving the time information, and encoding IRIG-B time code is formed, while with the device 485 to communicate via the
NCO
- 基于FPGA的DDS设计，通过外接DA转换器输出稳定的正弦波，方波和三角波，可单独产生时钟，不必借助硬件连接，包含寄存器程序，累加器程序和时钟发生电路等，以及顶层设计原理图-The DDS FPGA-based design, through an external DA converter output stable sine wave, square wave and triangular wave, can produce a single clock, without the help
d_clock
- 基于QUARTUSII，电子时钟，可用，VHDL以及原理图。-Based QUARTUSII, electronic clock, available, VHDL and schematic.
LCD1602
- Verilog 语言 CPLD 控制液晶自定义输出程序，可仿真，可转换电路原理图。-Verilog language CPLD control LCD custom output procedures, can be simulated, can be converted to circuit schematics.
max41a
- 用原理图方式实现4选1多路选择器，进行编译、综合、仿真测试等步骤-Schematic ways with 4-to-1 multiplexer, compile, synthesis, simulation testing and other steps
VHDL-qiangdaqi
- VHDL语言实现的抢答器功能，源码和原理图都包含在文件内，可以直接在FPGA上运行。-The VHDL Responder function, source code and schematics are included in the file, you can run directly on the FPGA.
i2s_input
- 基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真-FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment
USB_Blaster
- FPGA下载工具的原理图，可以自己做，了解真正的下载-FPGA download development
cnt100
- 一百进制计数器，采用层次化设计，底层文件为十进制计数器，顶层文件原理图设计-the procedure is based on vhdl,it can count 100,and use top-down
voter7
- 七位表决器，在QuartusII 13.0中，使用原理图输入，分模块设计，并带有仿真波形-Seven input voters,Designed in QuartusII 13.0,using schematic input design, Three module design, and simulation waveform
yima
- 用VHDL语言和原理图设计方法混合设计一个计数译码显示电路-Using VHDL and schematic design to design a method of mixing count decoding display circuit
99multiply
- 99乘法表,VHDL编写，原理图和代码齐全，仿真和DE2板子都经过测试，可成功运行-99 multiplication table, write by VHDL, simulation and DE2 board have been tested to run successfully
Graphic-design-
- 基于QUARTUSII图形输入电路的设计 1、 通过一个简单的3—8译码器的设计,掌握组合逻辑电路的设计方法。 2、 初步了解QUARTUSII原理图输入设计的全过程。 3、 掌握组合逻辑电路的静态测试方法。 -Graphic design QUARTUS II based on the input circuit
The-basic-design-of-the-flip-flop
- 1、了解基本触发器的工作原理。 2、进一步熟悉在Quartus II中基于原理图设计的流程。 - The basic design of the flip-flop
ax516_20150304A
- 黑金ax516开发板原理图20150304A，需要的同学赶快来下吧。-Black Gold ax516 development board schematics 20150304A, students need to hurry to the next bar.
yiweijicunqi
- 移位寄存器的原理图设计，基于quartusII软件。-Shift register schematic design, based quartusII software.