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110detector_lab
- 一个简单的探测110三位的探测器，用逻辑图和vhdl描述，包括实验报告和测试图。-a simple survey of 110 three detectors, and a logical map vhdl descr iption, including reports and experimental test plan.
交通灯实验报告
- vhdl交通灯实验报告-VHDL traffic lights Experimental Report
ClkDiv_2p5
- 2.5分频器。算是小数分频的一个例子。我们以前做实验的时候用来写实验报告滴~还有好多呢，慢慢上传吧~
lift_controler-verilog
- 用verilog写的电梯控制器，内附测试文件和实验报告
mimasuo
- vhdl 实验报告 verilog rs触发器 vhdl实验 vhdl 实验 报告 verilog rs触发器 vhdl实验
数字频率计实验报告
- 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter,
shuzi.rar
- 数字电子钟设计，整点报时，时分秒分模块设计，另附实验报告和实验结果，内容详细不容错过,The design of digital electronic clock, the whole point of time when minutes and seconds sub-module design, an additional test reports and laboratory test results, the details not to be missed
shixian.rar
- 该文件是一份本人设计的实验报告，报告内详细说明了用VHDL语言，设计一个三位动态显示的计数器。采用模块化得设计，设计通过了仿真以及下载实现。总的文件是：shixian.vhd,下面包括四个元件：jishu1000.vhd,xzqh.vhd,senvedec.vhd,disp.vhd.,this paper uses vhdl to complement a design about how to make three leds display at the same time.
FPQ.rar
- VHDL实现分频器 有仿真图 有实验报告,VHDL simulation of the realization of crossovers have the report there were experimental
FPGA-and-DS18B20
- FPGA与测温芯片DS18B20的通信实现，用verilog语言编写。有实际验证过的工程，有实验报告，有DS18B20的资料，适合快速了解。-FPGA chip with the DS18B20 temperature achieved with verilog language. Verified with the actual project, there are experimental reports, the DS18B20 data for quick understanding.
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
EDAreport
- 用VHDL实现秒表功能，即使时间为60分钟，实验报告格式，代码在文档最后。仿真软件使用quartus2-Using VHDL stopwatch function, even if the time is 60 minutes, the test report form, the code at the end of the document. Simulation software use quartus2
shuzizhong
- 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, d
jishuqi
- 本文十一个计数器的实验报告，阐述了设计的思路，设计的具体方案，以及上机操作的步骤，描述非常详细！-This article counters 11 Experimental report on the design ideas, design specific programs, as well as steps on the machine, described in great detail!
MyProject
- 3-8译码器的仿真实验。本实验选用的仿真开发软件是MAX+plus II Version 9.3，原理图源文件保存在MyProject目录中，为138decoder.gdf，另有我写的实验报告，呵呵，适合仿真入门-3-8 decoder simulation. Selected in this experiment simulation software is MAX+ Plus II Version 9.3, schematic source files stored in the MyPro
745221frequency
- 用Verilog HDL / VHDL实现的数字频率计（完整实验报告）-Using Verilog HDL/VHDL realization of digital frequency meter (complete test report)
Lift
- VHDL编写的6层电梯控制器，可在Altera的CPLD系统运行实验，内附实验报告-VHDL prepared 6-storey elevator controller in Altera s CPLD system experiment, experimental report containing
plj
- 设计数字频率计的程序及实验报告，可直接仿照本程序进行设计-Designed Digital Cymometer procedures and experimental reports, can be directly modeled on the process design
EDAVHDLTRAFIC
- 交通灯的EDA设计，完整的实验报告，适合那些做交通灯实验的同学参考-EDA design of traffic signals and complete the experimental reports, traffic lights do for those students experiment reference
dianti
- 用verilog写的电梯控制器内附测试文件和实验报告 -Use verilog to write elevator controller with the test documentation and test reports