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digital-clock
- 基于FPGA的数字时钟设计，时钟可以按设定好的时间进行自动计时，FPGA板子上可以显示相应的时钟数字，是数字电路课程的一个课程设计，也是对于VHDL语言的一个熟悉过程.-FPGA-based digital clock design, the clock can be a good time to set automatic timing, FPGA board clock can display the corresponding figure is a digital circuit des
shuzishizhong
- 这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。-This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.
digital_clock
- FPGA数字时钟，基于verilogHDL-FPGA digital clock, based verilogHDL
pcf8563
- pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示-pcf8563, written in quartusII VERILOG digital clock program, eight digital display
Example22
- 设计了一款基于多功能数字时钟的小程序，产生1Hz时钟的分频计数器并正常运行-Based on a small program designed multifunction digital clock divider to generate 1Hz clock counter and running
EDA-clockr
- EDA技术之数字时钟，带有定时闹钟功能-The EDA technology digital clock, alarm clock with timer function. . . . . . . . . . .
clock
- 基于FPGA的一个数字时钟的实现，还有硬件仿真，需要用quartusii_60_sp1_web_edition软件实现。-FPGA-based implementation of a digital clock, as well as hardware emulation, you need to use quartusii_60_sp1_web_edition software.
clock
- 数字时钟 LCD1602显示 可以校时。 编译环境QUARTUS II 7.2 -Digital clock LCD1602 display can be corrected. Compilation environment QUARTUS II 7.2
shuzishizhong
- FPGA代码，数字时钟，可调小时，分钟，秒钟，调节时闪烁-digital clock
12
- 用Verilog语言编写的数字时钟程序-Using Verilog language digital clock procedures!!!!!!!!!!!!!!!!!!!!!!!
digital_clock
- 本实验设计一个能够显示时、分、秒的数字时钟，时间在七段数码管上显示，显示数字为十进制数。通过开发板上的按键调整数字时钟的时间，分别用四个按键来控制分、时的增减，对于分、时的调整只影响本位，不产生进位或借位。各按键及数码管的功能要求如表1 所示。需要特别说明，因为开发板数码管的显示位宽不够，因此，通过一个开关进行切换选择（如：开,显示时分；关,显示分秒）。-When this experiment to design a display hours, minutes, seconds, digit
lcd
- fpga开发板实现lcd1602显示屏显示数字时钟。开发板测试通过-FPGA development board to achieve LCD1602 display digital clock. Through the development board test
mathtime
- 数字时钟maxplusii的实现，融合了VHDL与数字电路的内容，可自己添加一些自己想要的比如说彩灯，正点报时等功能-Digital clock maxplusii implementation combines the contents of VHDL and digital circuits, some of you want to add your own lantern, punctual timekeeping functions, for example
Timer_New
- 数字时钟，24小时显示功能 但是清零有问题-Timer for vhdl
shuzizhong
- 基于CPLD的智能数字时钟VHDL设计，能实现时钟、秒表、闹钟、定时等功能-ntelligent digital clock CPLD VHDL-based design enables the clock, stopwatch, alarm clock, timer, and other functions
clock
- 基于FPGA的数字时钟设计,本人试过，能用。-FPGA clock
superdigitalclock
- 这是基于FPGA开发板BASYS2的一个智能数字时钟，可以分3种模式：分钟，秒，百分之一秒。通过button切换模式并显示在数码管上-This is based on the FPGA development board BASYS2 a intelligent digital clock, can divide three patterns: the minutes and seconds, of a second.Through the button switch mode and in d
timeclk
- 数字时钟数码管显示时分秒，每一个小时蜂鸣器响2秒，课程设计，验证通过-Digital clock digital display minutes and seconds, every hour the buzzer 2 seconds, curriculum design, verification by
clock_18b20
- 基于lcd1602的温度计和数字时钟,包含详细的代码解释和实现方式-Lcd1602 based thermometers and digital clock
TIMER
- 用Verilog语言模拟的数字时钟的功能，时分秒工能都有，适合做毕设，完整工程-Verilog language simulation of the digital clock function, the time of the second division of the work can be, for the completion of the project, complete