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count10
- 10进制计数器,用于一般的计数、计时等基本元件。-ten counter
cnt24
- 24进制计数器，实现了电子时钟小时位的24进制计数-24 hex counter
counter
- 用vhdl语言，在QuartusII下，时序逻辑电路设计（带置位的异步可逆（加1或减1）6进制计数器）-With vhdl language, in QuartusII under sequential logic circuit design (set asynchronous reversible (plus or minus) hexa counter)
word
- 英文显示电路显示0到f 的十六进制计数器-English display circuit
COUNT60
- 60位进制计数器 可将程序下载后进行60进制表现 并应用于电子表运算-60 binary counter can download the program and after the performance of 60 binary operations used in electronic form
cnt16
- 含同步置零异步预置数功能的16进制计数器的VHDL实现，程序尽量简化，无冗余-16 counter VHDL implementation
cntm60v
- 基于VHDL的60进制计数器代码，可以实现六十进制计数-60 binary counter based on the VHDL code can be achieved sexagesimal counting
6counter
- 六进制计数器，输入必需是二进制数.用555定时器来产生1HZ的信号脉冲，作为CP的输入信号-Hex counter, enter the required binary number. 1HZ signal pulse 555 timer to generate the input signal as the CP
scr
- 60进制计数器同步置位30异步复位 modelsim仿真代码含激励 自己写的 可用 仅供参考入门-60 binary counter 30 the asynchronous reset modelsim simulation code containing motivate yourself to write synchronization set can be used for reference only entry
lkl
- 用门电路搭起来的13进制计数器，在7的时候有一个灯显示，初次提交，不对不处请指教-13 binary counter, gate ride up at 7 when a light display, the initial submission, please enlighten wrong not at
Counter10
- 在quartus 9.1软件上用verilog语言编写的10进制计数器程序-The Verilog language quartus 9.1 software 10 binary counter program
EDA-xiti
- 由12进制和60进制计数器组成的时钟电路。-12 229 and 60 binary counter clock circuit.
cnt4
- 4位2进制计数器，可以灵活组装成任意位数的2进制计数器-4 binary counter, can be flexibly assembled into arbitrary digit binary counter
counter10
- verilog编写的10进制计数器，并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
lqz3
- 这个程序是带置位的同步可逆（加1或减1）5进制计数器-This procedure is reversible with synchronous set (plus one or minus one) 5 binary counter
EDA-experimental-guide-book
- 利用QUARTUS II 8.1软件进行简单的EDA设计。该实验指导书原理阐述清楚，内容详尽，实验过程描述清楚，每一个实验步骤都有具体的截图。该实验指导书包括四个基本实验：实验1 QUARTUS II 8.1软件的使用；实验2 图形法设计24进制计数器；实验3 60进制计数器；实验4 简易数字钟。-Use QUARTUS II 8.1 software for simple EDA design. The experiment instructions Rationale clear, deta
CNT10
- 通过Quartus II 软件，VHDL语言实现10进制计数器-Achieve 10 binary counter
VHDL-code
- 使用VHDL语言进行门电路，优先编码器，译码器，各进制计数器，数码管显示的编写，在QUARTUS ii上模拟可用-Gates using VHDL language, priority encoder, decoder, each binary counter, write digital display, analogue available on QUARTUS ii
shuzizhong
- 数字钟，校时较分，显示,用元件例化写的vhdl文件，两个24进制，1个60进制计数器-Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter
CNT10
- 用VHDL编写的10进制计数器，教学实例内容，在Quartus II 8.1下编译成功。-Using VHDL 10 binary counter, teaching examples content in Quartus II 8.1 compiled successfully.