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verilog1
- 基于FPGA的多功能数字钟Verilog设计2007-06-17 21:06基本功能： 1．具有时、分、秒计数显示功能（6位数码管构成），以24小时循环为计时基准。 2. 具有调节小时、分钟的功能。 3．具有整点报时功能，整点报时的同时数码管显示闪烁提示。
Verilog_Digital_System_Design
- Verilog digital System design 2007 second edition
Experimentalboardschematics
- EACF型FPGA实验开发板原理图，中国科学技术大学EDA实验室@2007
atom.2007.12.tar
- Cores are generated from Confluence a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C
DSP_design_based_on_FPGA
- 用FPGA设计DSP,2007年上海FPGA高级研修班清华博士贺光辉讲义-FPGA Design with DSP, 2007 in Shanghai FPGA advanced training classes Tsinghua notes Dr. He Guanghui
data_system_design_based_on_FPGA
- 用FPGA設計数字系统，2007年上海FPGA研修班王巍老师讲义-Digital System Design using FPGA, FPGA Shanghai in 2007 Wang Wei, a teacher seminar handouts
DE2_schematics
- Altera FPGA DE2的原理图,相信有很大的帮助,经典的FPGA设计电路及相关的接口都有了。-Altera FPGA DE2 the schematic diagram, I believe there is a great help, classic design FPGA circuits and related interfaces have.
2007
- 本数字示波器以单片机和FPGA为核心，对采样方式的选择和等效采样技术的实现进行了重点设计，使作品不仅具有实时采样方式，而且采用随机等效采样技术实现了利用实时采样速率为1MHz的ADC进行最大200MHz的等效采样。-The digital oscilloscope and a single-chip FPGA as the core, the choice of the sampling methods and the equivalent sampling technique designed
vhdl-2008-just-the-new-stuff-systems-on-silicon.r
- VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL
MIT_Press_Circuit_Design_with_VHDL(2007)
- MIT Press出版的，书名是Circuit Design with VHDL(2007)，相信很有用的-MIT Press- Circuit Design with VHDL(2007)。It is of great importance for you!
Wiley[1].Advanced.FPGA.Design.Jun.2007
- a good book on fpga. useful for beginners
ThetrainingcourseofXilinxcompany
- xilinx公司2007年上海培训课程资料，主要是PPT。非常好的资料-xilinx Shanghai in 2007 training material, mainly PPT. Very good information
lcd_driver_projectComplete
- LCD CONTROLLER -- File name : lcd_driver.vhd -- -- Project : EE367 - Logic Design (Spring 2007) -- LCD Driver -- -- Descr iption : VHDL model LCD Controller Using State Machines -- -- Author(s) : Clint Gauer -- Montana State Univers
Wiley.Advanced.FPGA.Design.Jun.2007
- Advanced design for VHDL language
2007_Xilinx
- 2007年Xilinx 联合实验室主任会议 FPGA设计时序收敛-2007 meeting of directors of Xilinx FPGA Design Joint Lab timing closure
mahponk-2007-08-28
- Verilog code for pong on VGA
DE2-usb-isp1362-2007-08-18
- USB host project with Altera DE2
098111__1367421625730
- DE2_System_v1.4a.zip 71.2M 2007- 02 22:51 For DE2 boards with Serial Number (S/N) starting with Digit 0 and QuartusII version 6.0 DE2_System_v1.4b.zip 79.4M 2007-07-11 22:42 For DE2 boards with Serial Number (S/N) starting with Digit 0
DE1_D5M
- // --- --- --- --- --- --- --- --- --- --- --- -- // Copyright (c) 2007 by Terasic Technologies Inc. // -------------------------------------------------------------------- // // Permission: // // Terasic grants permission to use and mod