搜索资源列表
xor_mul
- 使用列表法，VHDL语言实现的基于多项式基的有限域乘法器，用于AES算法等对有限域乘法有要求的算法
AES加密的VHDL源码
- 用VHDL语言实现的AES加密算法的源代码，已经在硬件上下载运行实现了。
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
AES256-XILINX10.1
- 用XILINX公司提供的NetFPGA板卡并结合软件Xilinx10.1进行系统设计，采用硬件描述语言Verilog实现了 AES-256加密算法。-Provided by XILINX board combined with software Xilinx10.1 NetFPGA system design, using Verilog hardware descr iption language implementation of the AES-256 encryption algorit
AESverilog
- AES加密算法的Verilog语言实现，通过编译-AES encryption algorithm in Verilog Implementation
AES-algorithm-design
- 基于FPGA的AES算法芯片设计实现,文中具体给出了测试的运行时间等数据-AES algorithm for FPGA-based chip design to achieve
1
- 一种基于FPGA的AES算法的低功耗实现,对于AES低功耗设计有帮助作用-FPGA-based AES algorithm to achieve low power consumption, low-power design for the AES helpful
aes-core
- Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
AES
- 利用verilog HDL实现的AES算法，在密码芯片加解密中显示出了突出的优越性-The reference-AES.V which has been uploaded is particularly useful for researchers who are dedicated to the password-chip researching.
base-on-FPGA-AES-addkey-design
- 介绍了用FPGA实现AES算法所用的开发工具，开发语言和所选用的芯片，及AES算法的硬件实现方式。着重阐述了AES算法FPGA实现的总体设计框图，并副有部分源代码- introduce design tool,language and core of AES which base on FPGA,and AES hardware design.
FPGA--AES-algorithm
- 本文介绍了AES 数据加密结构, 以及相关的有限域的知识及简单运算, 提出了一种用FPGA 高速实现AES 算法的方案, 该方 案设计的加密模块支持AES 标准的三种密钥长度: 128,192,256, 支持ECB, CBC, CTR 三种工作模式, 即支持feedback 和non- feedback 两种模式, 最后给出了本设计的性能指标-This article describes the AES data encryption structure, as well as the
aes
- aes加密算法的Verilog语言实现（顶层代码，已编译，无错误）-aes encryption algorithm of Verilog language (top-level code, compile, no error)
aes_verilog
- AES算法的Verilog实现，简单易懂-Verilog implementation of the AES algorithm, easy-to-understand
AES_verilog
- 对AES算法加密解密的Verilog源代码，可以实现其128位和256位明文密文之间的转换。-AES algorithm for encryption and decryption of Verilog source code, can achieve the conversion of its 128 and 256 between the plaintext ciphertext.
AES
- AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.
AES
- AES加密和解密算法的硬件语言描述，很值得大家来学习！-AES hardware encryption and decryption algorithm descr iption language, it is worth learning!
AES
- AES算法部分模块行位移列变换以及主题程序加密解密-AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program
各种密码算法的FPGA实现情况
- 各种密码算法的FPGA实现情况 1.AES算法FPGA实现分析 2.DES加密算法的高速FPGA实现 3.RSA加解密运算的FPGA硬件实现研究(FPGA implementation of various cryptographic algorithms)
AES算法硬件实现
- AES算法硬件实现，使用SAKURA开发板，128位密钥的AES算法