搜索资源列表
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
CoreAES128
- Full AES Simulation Code
AES!
- AES algorithm very good code tested in xilinx ise tool
sbox
- verilog code for s-box generation for AES algorith
09912007AEScoremodules
- aes descr iption architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
AES_enc_core_tb
- this code discribers testbench for aes algorithm. it is written by .vhdl
aes-core
- Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
CC2430
- CC2430基础实验源代码，帮助读者快速认知CC2430芯片 ││sch_CC2430ZDK.pdf ││ │├─1.LED │├─2.LCD │├─3.Clock模式 │├─4.External中断 │├─5.Timer中断 │├─6.Stop观看 │├─7.ADC │├─8.Temp传感器 │├─9.Joystick │├─10.UART - 液晶 │├─11.DMA │├─12.ADC_Series │├─13.Flash写作
aes-vhdl
- this file contains vhdl code for aes
aes
- AES is a code encryptioin function after RC5.
aes
- aes加密算法的Verilog语言实现（顶层代码，已编译，无错误）-aes encryption algorithm of Verilog language (top-level code, compile, no error)
aes_pipe
- 流水线AES加密VHDL代码，代码规范，值得参考- The VHDL code of Pipelined AES encryption
new
- vhdl code aes algorithm newly modified
AES
- AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.
aes
- contains AES doc with code in Verilog
AES
- AES的加密解密verilog全部源代码-AES encryption and decryption verilog full source code
aes-master
- aes master by vhdl code and decode
aes128-hdl-master
- Verilog AES hdl key 128 bit code and decode
aes_128pprm3
- 基于PPRM3S盒的128位AES密码算法Verilog代码(Verilog code for 128 bit AES cipher based on PPRM3S box)