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DM412_1ea_test
- 点晶DM412单颗级联测试程序，使DM412输出恒流，修改级联数可做点光源控制程序-DM412 single point crystal cascade testing procedures so that the output current DM412, modify the number of cascade control procedures can point light source
BlockRAM
- xilinx BlockRAM 级联，利用Xilinx原语（非IP Core），更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
cordic_generic
- 本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法，并且在原始的级联型的基础上编写的循环(iterative)型的cordic,可通过generic配置。带一个不可综合和可综合的testbench(for altera)。稍微改动可应用于xilinx fpga-a generic synthesizable cordic with 2 modes: cascade and iterative. based on opencores.org version,
CPU
- 本人主要是介绍CPU和运算器级联的程序，采用的是VHDL语言-I was to introduce the CPU and the main computing device cascade process, using the VHDL language
cascaded_adder
- implementation of cascade adder with verilog plus testbench
casacade_leds
- Alter kit FPGA de2-35 This project shows a cascade motion through board leds.-Alter kit FPGA de2-35 This project shows a cascade motion through board leds.
pipeline
- 用流水线构成的串行八位加法器，可以输出进位级联-With a line consisting of eight serial adder, can output binary cascade
seg_led_display
- 数码管灯控制程序，动态扫描过程。硬件连接方式比较特殊，位选单独控制，又是级联方式。6个数码管。-Digital tube light control applications, dynamic scanning process. Hardware connection is rather special, separate control of Choice, but also a cascade. 6 digital control.
six_led_display
- 数码管灯控制程序，动态扫描过程。硬件连接方式比较特殊，位选单独控制，又是级联方式。6个数码管。-Digital tube light control applications, dynamic scanning process. Hardware connection is rather special, separate control of Choice, but also a cascade. 6 digital control.
shuzixiabianpin
- 数字下变频中cic滤波器，级联三级，主要功能是抽取滤波，及重要参考资料，包括数字下变频论文-Digital down conversion of cic filter, cascade three-level main function is to extract the filter, and important reference materials, including digital down conversion papers
CascadeCounter
- 一个基于Spartan3E的级联计数器，通过验证可用-A cascade of counter-based Spartan3E, available through the validation
Lab_intro2_ayjh
- A code to develop a cascade of counter
AD420
- SPI控制三片AD420程序，三片AD420级联，其输出电流是0-20mA-SPI control three AD420 program, three AD420 cascade, the output current is 0-20mA
jishuqi
- EDA课程实验计数器 16位基本计数器 并可简易级联为48位 96位计数器-EDA course experiment the basic counter and 16-bit counter cascade of simple 48-bit counter 96
verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
FIR
- 级联优化的半带插值滤波器，分模块设计-Half-band interpolation filter cascade optimization sub-module design.
Comparador
- its a comparator of 4bits with ins cascade-its a comparator of 4bits with ins cascade
fir_lms-adaptive-filter
- 采用VHDL语言编写的fir级联结构的LMS自适应滤波器，方便学习研究自适应滤波器有关参数实际实现的影响-Using VHDL language fir cascade structure of LMS adaptive filter, adaptive filter to facilitate study and research the impact of the actual implementation of the relevant parameters
adder4
- 基于VHDL的4位加法器。 由4个一位全加器级联构成。-VHDL-based 4-bit adder. One consists of four full adder cascade.
PtDdcCic3
- CIC三级抽取滤波器源代码，包括modelsim的仿真代码，已经测试过稳定性-cic 3 cascade filter source code， including modelsim simulation code， and test