搜索资源列表
DCT_vhdl
- IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable-IDCT-M is a medium speed
ca
- 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
dtmf
- dtmf 8880 tx phone ca-dtmf 8880 tx phone call
bcd2_7ca
- VHDL unit for 7-segment (CA) driver.
m_ca7
- verilog编写的基于CA算法的m序列发生器，其中验证了多种CA系数来实现m序列。-CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.
CAcode
- 这是一个产生CA码的程序,fpga使用,VHDL编写-This is a generated procedures of the CA code, fpga uses to write the VHDL.
xiangmu_chengxu
- 雷达基本恒虚警处理，CA-CFAR(单元平均恒虚警处理),OS-CFAR（有序类恒虚警处理）,SO-CFAR（选小类恒虚警处理），-radar basic constant alarm operation,obtaining os-cfar,so-cfar,os-cfar,ca-cfar
CA-CFAR
- CA CFAR Algorithm implementation in FPGA
TEC-CA-experimentprocedure
- TEC-CA学生实验指导书 1.TEC-CA 介绍 2.调试软件DebugController的介绍 3.计算机组成原理实验详解 4.vhdl语法介绍-Of TEC-CA student experiment instructions 1.TEC-the CA describes the introduction of the debugging software DebugController. Principles of Computer Organization exper
ca_code_VHDL
- 本程序是ca码的FPGA产生程序，希望在此能够给与大家共享-This program is ca code generated by FPGA program, I hope to give everyone shared this
Gps_c_code_nco
- 在GPS接收机本地NCO及CA码产生，生成超前码，即时码和滞后码。-generate NCO and ca coce in gps receiver，generate E_P_L code.
rom_mem
- 设计14×6 位的ROM，其结构图如图1 所示。其中，reset 为复位按钮，可以采用TEC-CA 平台上的复位脉冲，对应ACEX1K100 型号芯片的管脚ID 为83，Cyclone 的则为240；clock 为时钟脉冲源，可采用TEC-CA 平台上单脉冲按钮，对应ACEX1K100 型号芯片管脚ID 为 79，Cyclone 的则为29；dout 为ROM 单元的输出引脚。-Design 146 of the ROM, the structure shown in Figure
asynram
- 设计32×6位的RAM，其结构图如图2所示。其中，adr为地址引脚，cs、wr、rd分别为片 选、写和读引脚，din_out为输入输出引脚。当cs=0且wr由低到高（上升沿）时，din上的输 入数据写入adr指示的单元中；当cs=0且rd=0时，adr对应单元的数据在dout数据线上读出。 因wr在上升沿时写入数据，因此可以采用TEC-CA平台上的单脉冲按钮作为wr。-Design 326 of RAM, the structure shown in Figure 2. Which,
CA-code
- 生成CA码verilog代码，quartusII开放环境，含源代码和仿真文件（波形、testbench）-CA generated code verilog code, quartusII open environment, including source code and simulation files (Waveform, testbench)
CPU
- 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware descr iption language developm
rk153
- You can get a very accurate amplitude, frequency, phase estimation, It contains CV, CA, Single, current, constant turn rate, turning model, A very useful program.
dg137
- Based on matlab GUI interface design, It contains CV, CA, Single, current, constant turn rate, turning model, Simulation of the effect is very good.