搜索资源列表
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
OCM12864
- 含有12864LCD 的正确使用方法，以及指令的设置-12864LCD contain the proper use of methods, as well as set up commands
yonghuzhiling
- FPGA开发入门实验，一个SOPC开发实例——用户指令的设计，希望对对学者能有所帮助-Introduction to FPGA development experiment, an example of SOPC development- the design of user commands, in the hope that scholars can help
proc
- vhdl processor,5 commands,memory,testbench
modelsim_cmd_ref_ug
- Mentor Graphics ModelSim Reference Manual Software v6.3g。图形界面Modelsim仿真说明手册，对工具及命令说明非常详细。官方资料-Mentor Graphics ModelSim Reference Manual Software v6.3g. Graphical interface Modelsim simulation instruction manual, instructions on the tools and commands
OpticalFiber
- 利用VHDL语言编写的光纤通信，将上位机的命令通过主站处理后，用光纤发送到从站。-VHDL language using fiber-optic communication, the host computer commands through the main points are treated, the fiber is sent to from the station.
mc55
- mc55模块功能介绍，使用说明。详细介绍了模块功能及命令！-mc55 module features introduced for use. Details of the module functions and commands!
iso_rfid_send
- 15693协议的发送模块，能够完成数据的发送，并且在特定的情况下发送错误指令，功能单一，可以完成16位数据的发送。-15693 protocol to send the module, to complete the data transmission, and in certain circumstances to send error commands, single function, you can complete the 16-bit data transmission.
sdram
- 通过 UART 读写 SDRAM verilog 源代码 通过 UART 的接口发送命令来读写 SDRAM 命令格式如下： 00 02 0011 1111 2222 00： 写数据 02： 写个数 0011： 写地址 1111 2222： 写数据， 是 16 bit， 每写完一个数据，向串口发送 FF 回应； 输出： FF FF 01 03 0044 01: 读sdram 03： 读的个数 0044: 读的地址 输出： xxxx xx
traffic-light
- 一个单片机的多任务操作系统写的交通灯控制程序，该程序在单片机开发板上运行正确，可通过PC机的串品发送指令进行控制，程序附有中文注释。-A single chip multi-tasking operating system written in traffic light control program that runs right in the microcontroller development board, PC-string by sending commands to contro
1602jtxs
- 1602液晶显示器的头文件，主要功能是进行lcd的初始化，及写指令、写数据、检测忙碌状态、读数据、输出字符和字符串子函数程序。主函数中写出显示的光标地址和要显示的字符串就可进行仿真。用于初学lcd的朋友，可进行简单的显示字符串。-1602 LCD header file, the main function is to carry out lcd initialization, and write commands, write data, detect busy state, read dat
awg
- 基于FPGA的任意波形发生器源代码，并且添加了上位机发送指令和数据（低八位用来发频率控制字，高八位用来发指令）。-FPGA-based arbitrary waveform generator source code, and add the host computer to send commands and data (low eight frequency control word is used to send high eight used to send commands).
IO-Port-Programming
- 8051 source code for understanding I/O port operation and commands
Verilog--classic
- verilog 的经典教程，包含基本命令定义等内容并且由实例讲解了具体的编程方法和设计思想-Verilog classic tutorials, include basic commands the content such as defined by example and explain the specific programming method and design thought
MIPS_Pipelined_CPU
- MIPS Pipelined CPU written on VHDL with commands, 5 stage pipeline
ad_max11046
- 基于nios2系统的mx11046的初始化，采样，写命令，读数据，以及一些优化设置。-Based on mx11046 nios2 system initialization, sampling, write commands, read data, and some optimization Settings
cpu
- 8位实验CPU设计利用设计好的指令系统，编写汇编代码，以便测试所有设计的指令及指令涉及的相关功能。设计好测试用的汇编代码后，然后利用Quartus II软件附带的DebugController,编写汇编编译规则。接着，利用DebugController软件把汇编编译之后的二进制代码置入到所采用的存储器中，并对设计好的8位CPU进行测试。-Eight experiments designed CPU design using the instruction set, write assembly
modelsimPdebussy-batch-processing
- 内容包括采用Windows批处理方式高效执行Verilog仿真验证的方法，采用Modelsim+debussy联合仿真，里面包含一个加法器实例，批处理文件，仿真指令等。-Included with Windows batch efficient implementation of Verilog simulation method, using Modelsim+debussy co-simulation, which contains an example of an adder, batch
cpld_uart_TXRX
- max2 cpld 开发的vhdl 完整串口通信程序，TXRX可同时收两个命令 带超时 600门-max2 cpld vhdl developed complete serial communication program, TXRX can simultaneously receive two commands with timeout 600
textfilereading2
- It is a VHDL code for the operation of file reading by IEEE commands which can transfer the multiplr data