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kuaijintuiyinyueshizhong_VHDL
- 本程序为模拟可校时的时钟程序;clk--时钟信号,rst--清零信号,set_en--校时 使能信号,faster--快进信号,slower--快退信号,hour--小时校时,min--分钟校 时,(hh,hl,ml,mh,sh,sl)--时,分,秒显示信号。 校时的时候,秒清零。
hh.rar
- 串行输入并行输出 用vhdl语言描述的 有源代码主打色,Serial input parallel output using vhdl language to describe the main color of the source code
hh
- 双口RAM的verilog描述 双口RAM的verilog描述-Dual-port RAM of the verilog descr iption of dual-port RAM of the verilog descr iption
hh
- ad1674的控制程序VHDL 利于初学者掌握AD新片的控制,实现了初始化,采集存储-AD1674 CONTROL VHDL
term-project
- this project is related with Goal of this system is applying some microprocessor knowledge with use C code on the hardware design. This project is calculating the body mass index value of a person on LCD screen and printing the BMI value. Program nee
112
- LED七段数码管数字钟具体完成功能: 1.设计并完成LED七段数码管数字钟电路。 2.数字钟显示格式为:HH:MM:SS。 3. 具有通过 开关能够调整时、分、秒的功能-led chengxu
hh
- 此文件是一个Butterworth IIR滤波器的VHDL程序,此滤波器是10阶的,通带频率在2.5MHz——7.5MHz,采样频率为200MHz。此滤波性能不是很好,仅供参考。-This file is the VHDL program in a Butterworth IIR filter, this filter is 10 bands, the frequency of the passband of 2.5MHz- 7.5MHz sampling frequency is 200MHz
fpq
- 分频器源码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY fpq IS PORT(clk:IN STD_LOGIC clk_out:OUT STD_LOGIC) END fpq ARCHITECTURE hh OF fpq IS CONSTANT m : INTEGER:= 5 SIGNAL tmp:STD_LOGIC BEGIN PROCESS(clk,tmp) V