搜索资源列表
xilinxIDE
- xilinx fpga 下的IDE控制器原代码,贡献一起学习-xilinx fpga controller under the IDE source code and contribute to study together
ide
- ide 的HDL描述.有接口和时续-HDL descr iption of the ide. when there is interface and continued
SOPC_NIOS_TEST
- ALTER+NIOS II+SOPC_Builder+NIOS II IDE例程（VHDL）-ALTER+ NIOS II+ SOPC_Builder+ NIOS II IDE routines (VHDL)
Nios_II_SPI
- 本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is
NovakodStudio
- For all thoses interested in a new language and programming paradigm. This is a complete IDE for programming in the psC - Parallel and synchronous C- Language. This language is a high level replacement for VHDL/verilog.-For all thoses interested in a
1
- 实现按键中断，在NIOS II IDE平台上实现按键中断，按键驱动程序在Quartus ii里面用VHDL编写。-interrupt
pwm
- 利用Verilog语言产生17路PWM波，控制17路舵机，可以作为IP核添加到AVALON总线上，在nios IDE里用C语言控制。-Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with the C language.
Verilog000
- FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，调试板子各模块功能。-Verilog语言的学习，熟悉Verilog语言的各种语法。 ②、FPGA的学习，熟悉
xie
- 通过IDE接口实现硬盘扇区的写操作，DMA方式的源代码-write operation to hard disk sector through the IDE interface , DMA mode of the source code
du
- 通过IDE接口实现硬盘扇区的写操作，DMA方式的源代码-write operation to hard disk sector through the IDE interface , DMA mode of the source code
asjggsldawendang
- 基于VHDL语言的硬盘控制器的设计，IDE开发使用的文档！-Based on the hard disk controller VHDL language design, IDE developed using the documentation!
IDE_VHDL
- 此代码为wishbone公司的IDE协议主机端VHDL源代码，有三个版本，实现了UDMA。版权归wishbone公司，请勿用于商业用途。-This VHDL codes with threr versions implemented IDE host protocol，supporting with UDMA。
CacheFromScratchFinalWeek_ise12migration
- VHDL implementation of an 8-bit multilevel cache. Produces timing diagrams when run on a suitable IDE such as Xilinx.
SOPC LED实验
- 通过Quartus II、SOPC Builder、Nios II IDE三种工 具的配合使用 用软件控制led，VHDL程序通过描述硬件电路控制led的依次亮灭(Through the Quartus II, SOPC Builder, Nios II IDE three workers With the use Use software to control led, VHDL program by describing the hardware circuit control l