vhdl 写的 PCI IP核程序，已经过测试-pci ip core

USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi

进行对数运算的IP核，可以计算以2，10，e为底的对数，最高可输入24bit宽度的数据。 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。(The IP kernel that performs logarithmic operations can compute data at the base of 2, 10, and E, with the highest input 24bit width. Written in AHDL language, can