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myproject
- 四位全加器,VHDL语言,max+plusII平台做的
MyProject
- 3-8译码器的仿真实验。本实验选用的仿真开发软件是MAX+plus II Version 9.3,原理图源文件保存在MyProject目录中,为138decoder.gdf,另有我写的实验报告,呵呵,适合仿真入门-3-8 decoder simulation. Selected in this experiment simulation software is MAX+ Plus II Version 9.3, schematic source files stored in the MyPro
MYPROJECT
- 芯片与FPGA的接口代码,实现以太网10兆的接口方案之源代码-CP2200 & FPGA
myproject
- 开发环境ISE,使用VHDL语言实现了任意整数分配的分频器,又有一个信号可以控制左转右转的流水等。-Development environment ISE using VHDL language to achieve arbitrary integer assigned crossover, there is another signal control Zuozhuanyouzhuan running water, etc..