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verilog-Perl-3.120.tar
- Verilog Parser in Perl
fracn09
- Clock generation perl to vhdl oijoij
all_packages_20080525.tar
- FMF VHDL Models All the FMF models are VHDL 93 and VITAL 2000 compliant and require the VITAL 2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We hav
perl
- perl学习资料，包含一些常用的一些文档，可直接做来用于实践-perl training
PERL_PROGRAM
- perl program for generating test vector and veryfying test vector useful for VHDL design verification
HowtousePerlinyourVerilogHDLDesignFlow
- use Perl in your Verilog HDL Design Flow,利用Perl语言方便管理Verilog HDL 代码。-How to use Perl in your Verilog HDL Design Flow
VerilogPreprocessing
- 使用 Perl语言 ,采用面向对象的编程 (OOP) 方法 ,讨论了一种 Verilog预处理工具的设计.-Using the Perl language, object-oriented programming (OOP) method, discussed the design of a Verilog preprocessing tool.
verilog_testbench_genetator
- 这是一个perl程序 只需要在cmd中运行，参数为你的Verilog名字 功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010---------------
Perl_for_CRC
- Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redu
testbench-from-perl
- 直接生成testbench的perl脚本-The software can produce test bench directly by perl
perl
- perl脚本的一些初步入门知识，对于以后熟练掌握帮助很大-perl scr ipt started some preliminary knowledge of great help for the future master
blif2vhdl-v1.1
- 将BLIF（Berkeley Logic Interchange Format）格式的电路转换为VHDL代码，使用perl编写，需要perl环境才能使用。 内含BLIF格式的官方说明。-Translate BLIF（Berkeley Logic Interchange Format）circuit to VHDL descr iption, the translator need perl environment to run. Please check you have related t
wb_uart_latest.tar
- 实现一个一16750/16550 UART。该UART内核是完全基于另一个OpenCores的项目：UART_16750塞巴斯蒂安维特。 请找到有关于UART内核的文档。 该接口是现在有8位Wishbone总线兼容。 随着GHDL模拟器只需运行： ./ghdl_uart.bat 使用任何其他模拟器，开始模拟以下perl脚本必须运行之前： uart_test_stim.pl> FILENAME.TXT 其中，FILENAME.TXT是通用的“stim_
crc_verilog_xilinx
- 包括下面文档： readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. cr