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8051-vhdl-code
- 单片机8051 IP内核的VHDL源码，需要的开发环境QUARTUS II 6.0。
learn_dds.基于quartus ii 9.0的简易dds波形发生器
- 基于quartus ii 9.0的简易dds波形发生器，可以产生正弦，方波，三角波，可变幅，可变频。非常适合学习使用，使用时请按自己的芯片和引脚设置,Quartus ii 9.0 Based on dds simple waveform generator can produce sine, square, triangle wave can be amplitude, frequency can be. Very suitable for learning to use, when used
DE2_SD_Card_Audio.DE2上SD卡的读写代码
- DE2上SD卡的读写代码，应用环境quartus ii,DE2 on SD card to read and write code
par_serial-and-serial_par-VHDL
- 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
DW8051.rar
- 一个兼容keil的8051内核，在Quartus II 8.0 上编译通过的。希望对大家有帮助！！,Keil a 8051-compatible core, the Quartus II 8.0, adopted by the compiler. We want to help! !
VHDL.rar
- 教你在Quartus II中如何实用LPM库，对与FPGA系统设计有很好指导作用,Teach you how to Quartus II in the LPM utility library, with the FPGA system design have a very good guide
DDC.rar
- verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。,Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.
communicate-with-the-computer
- 用Altera Quartus II 的VHDL语言完成的串口与电脑通讯的源代码-The use of Altera Quartus II VHDL language to complete the serial port to communicate with the computer source code
fpga-pwm
- 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
UART
- 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
clk_vhdl
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
ff
- QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。-QUARTUS II platform based on the VHDL language elevator system control procedures.
ADC0809
- 用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
stopwatch
- Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
sinbo
- 基于quartus II的正弦波发生器，可调频率相位，用其时序仿真即可显示，分模块设计的。有sin。mif文件.-Based quartus II of the sine wave generator, adjustable frequency and phase, with the timing simulation can show that sub-module design. A sin. mif file.
I2C
- 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。 仿真工具：modelsim 综合工具：quartus -Language:
TEST5
- 8位硬件加法器设计 熟悉Quartus II的VHDL文本设计流程全过程，学习简单时序电路的设计、仿真和测试。-eight bit Hardware adder design Familiar with Quartus II VHDL text design flow process, learn the simple sequential circuits design, simulation and testing
Quartus-II
- Quartus II的使用教程包括Quartus II的软件教程，VHDL语言的编程方法，实际工程项目等。-Quartus II tutorial covers the use of Quartus II software tutorials, VHDL programming language, the actual engineering projects.
FPGA_Quartus-II
- FPGA入门教程 简单介绍QuartusⅡ环境，如何在QuartusⅡ开发环境下进行FPGA硬件设计，开发流程以及建立VHDL等工程-FPGA Tutorial Brief introduction to the Quartus II environment, how the Quartus II development environment for FPGA hardware design, development process and the establishment of t
VHDL程序
- 利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)