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seg
- 一个时钟程序,还有跑表,感觉相当不错的,有需要就下载吧
seg
- 7段数码管显示的VHDL语言,适合初学者用,相当不错的
seg
- 自己做的开发板,基于epm7064slc44-10控制数码管显示0-F。有助于初学者学习。
lab4showTAs
- 4 seg display, button debouncer, and controller for parking meter
SSC
- Implement the 7 segment diplay on spartan 3
freq_meter
- Frequency meter Verilog implementation for Xilinx XC2C256. MT10T7 7-seg LCD used for output.
seg
- 用VHDL编写的数码管显示程序(数码管共用数据线),带有进制转换功能-Written in VHDL, digital tube display program (digital control shared data line), with a binary conversion
seg
- SEG ovladac na segmentovku
seven_lcd
- 七段数码管显示的时钟程序VHDL代码 ISE编译环境-SEVEN seg VHDL ISE CLOCK
seg
- 程序说明: 本次实验控制开发板上面的数码管。 \1-f文件夹里面的程序控制数码管从1开始显示,逐渐加1,一直到f。 \1234文件夹里面的程序控制数码管显示1234。 目录说明: 工程在\project文件夹里面 源文件和管脚分配在\rtl文件夹里面 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Descr iption: This development board above th
seg
- 数码管显示(verilog) 自己写的 在数码管上显示01234567 动态显示-Digital LED display (verilog) himself wrote in the digital tube display 01234567 dynamic display
speed_measure_on_7_segment
- Period method of frequency measuring (change constant to speed measure). DE2 Board Quartus project. Input signal on GPIO, result on 7seg, start/stop with key[0].
wodewenjian
- 基于FPGA的电梯控制系统的设计 将电梯的运行状态划分为开门,一层,二层,三层,四层五个状态,设一层开门为电梯的初始状态,up1,up2,up3分别作为一层,二层,三层的上升请求,四层没有上升请求;down2,down3,down4分别作为二层,三层,四层的下降请求,同理一层是没有下降请求的;s1,s2,s3,s4分别作为一层,二层,三层,四层的停站请求;x1,x2,x3,x4分别作为一层,二层,三层,四层的停站请求显示;door作为门的状态,“0”表示关,“1”表示开;mode作为电梯的运
seg
- 用verilog语言实现数码管控制工作,有问题可以qq咨询,516998649-use the verilog language to drive the seg
verilogiic1121
- i2c的verilog程序,通过写入eeprom再读出并在seg数码显示管上显示来进行验证-i2c' s verilog program eeprom read by writing out and in the seg digital display tube display to verify
seg
- verilog编写的时钟分频程序和数码管显示程序-verilog
lab9_0~60
- 顯示0~60的循環數,可顯示在SEG上方!-Showing 0 to 60 cycles, SEG can be displayed in the top!
seg
- 这是用verilog 编写的静态数码管实验,初级,实用,挺好的例程-It is written in verilog static digital test, primary, practical, very good routine
8-SEG-LED-Board
- 基于FPGA的EPM 1270芯片开发板的8 SEG LED Board Verilog程序,已通过测试,能正常使用,引脚已配好。-Based the EPM 1270 chip FPGA development board 8 SEG LED Board Verilog program has been tested normal use, the pin with a good.
spartan3E-seg-driver
- spartan3E seg display driver-spartan 32 seg display driver