搜索资源列表
serial
- rs_232 serial port logic
Serial.rar
- 基于MAX2运用Quartus实现串口通信,MAX2-based use of Quartus Serial Communication
parallel_to_serial.rar
- 一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据,A parallel to serial verilog source code you can transfer your parallel data to serial data.you have 12bits parallel data then you will have a serial data
par_serial-and-serial_par-VHDL
- 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
FPGA-URAT.rar
- FPGA与PC串口自动收发程序,verilog源程序,FPGA and the PC serial port automatically sending and receiving process, verilog source code
serial
- VHDL实现串口控制逻辑源代码,包括各个模块的具体实现和元件例化-Serial control logic to achieve VHDL source code, including various modules and components to achieve the specific cases of
标准的串口通讯设计VHDL
- 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme
vhdlad
- 基于VHDL的高速串行AD转换器控制设计与实现-VHDL-based high-speed serial AD converter control design and implementation
SPI_controller
- SPI serial flash ROM的verilog源代码, 针对winbond W25x16,已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SPI serial flash ROM in verilog source code for winbond W25x16, logic has been verified, and actually used in chip design, as a module to work.
NIOSII-uartprogram
- SOPC技术 NIOS II 串口使用详细资料-SOPC technology use NIOS II serial Details
serial
- 基于VHDL的串口通信 基于VHDL的串口通信-VHDL-based serial communication based on VHDL Serial Communication
top
- RS232串行通信，采用VHDL编程，由波特率发生器，接收器和发送器构成-RS232 serial communication using VHDL programming, by the baud rate generator, receiver and transmitter constitute
uart
- FPGA的串口模块，实现FPGA与PC机的串口通讯。-FPGA serial modules, FPGA implementation with the PC-Serial communication.
A_bit_serial_data_transmitter
- 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify th
dianziqin
- vb编写的电子琴，仿真实电子琴操作界面，包含与FPGA串口通信的功能。-vb prepared organ, electric piano emulation interface is included with the FPGA serial communication functions.
mux_reg
- VHDL code for a multiplexer and a parallel/serial in parallel/serial out shift register
Serialadder
- VHDL语言串行加法器 可以实现五位加法运算-Serial adder five addition operations can be achieved
serial
- 串行转并行的VHDL源代码，结构化编程，学习模块化编程和实用性都很大。-Serial transfer parallel VHDL source code, structured programming, modular programming and practical learning are great.
FIR-using-bit-serial
- 用bit serial方法设计来有限长冲击响应滤波器，并用FPGA实现验证-Designed to use bit serial finite impulse response filter, and verify with the FPGA implementation
serial
- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。 串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值 是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通 信同步.-The mo