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simple h264 vhdl encoder
- simple h264 encoder，source code and test code in vhdl，简单h264 硬件编码器，源代码及测试，vhdl语言
simple clock
- A simple clock with VHDL code.
5
- simple code based on verilog shifter , cla ,clg , ALU ,PC, decoder , tb_top
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising
CuFIFO
- fifo的vhdl代码,比较简单，适合初学。-fifo the VHDL code, is relatively simple, suitable for beginners.
61EDA_D1051
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
PROCESSOR
- PROCESSOR is a design with simple microprocessor implementation.
verilog_design_a_simple_cpu
- 用verilog设计一个简单的cpu系统-Verilog design with a simple cpu system
VHDL04
- 4位微处理器系统的顶层描述代码，本人亲自测试，代码很简单。明了。内容无毒。放心下载使用-4 top-level descr iption of the microprocessor system code, I personally tested the code is very simple. Clear. The content of non-toxic. Download ease the use of
miniuart.tar
- 用VHDL描述的简单UART接口，能正确实现简单的功能-VHDL descr iption with a simple UART interface
uart-vhdl-testbench
- simple uart vhdl behavioural model (package) vhdl testbench example
cpu
- 设计以及基本的CPU，至少包括四个基本单元，控制单元，内部寄存器，ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its perf
processor
- The purpose of this project is to design a simple Processor Unit
perjoko_ting_ting
- Simple Microprocessor built with XILINX ISE
Microprocessor_load_store
- Implementation of a simple microprocessor having a load-store architecture.
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
Simple-computer-design
- Simple computer design and implementation 简单计算器的设计与实现-Simple computer design and implementation
UART
- This vhdl code has a simple implementation of an UART receiver. This code was generated march 2011 as a universuty project
Simple-VHDL-tutorial
- VHDL simple tutorial Farsi
vlsi_MP3
- VLSI Design Laboratory A simple MP3 player design using VHDL