搜索资源列表
RD1006--I2C
- RD1006--I2C与存储器的IP 代码及说明文档，lattice提供，I2C Controller for Serial EEPROMs 源代码可用，并且包含tb文件-RD1006 -- I2C and memory IP code and documentation. Lattice offer I2C Controller for Serial EEPROMs source code available, and document contains tb -
trellis_verlog
- ATSC发送端部分，ATSC标准特有的TCM编码，共6个文件，包含tb文件，已通过仿真，没有问题，verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code
watch
- vhdl语言编写的一个秒表源码，包括在LCD上显示的部分，附带TB源码，对初学者比较实用
tb
- 检测上升沿的verilog程序，有验证程序，可用synplify验证
VGA
- 基于Verilog的VGA显示程序 用于实现FPGA对于VGA显示器的控制实现图像显示，并给出相关测试的TB文件-The VGA display program based on Verilog FPGA for implementing the control of the VGA display Image display
minicore
- minicore为一个加法器的最小结构，含有移位RAM 和调试的TB 程序等。-minicore for a minimum adder structure, containing translocation TB of RAM and debug procedures.
masterdecoder
- AHB总线协议 Master实现代码，对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
TB_VHDL(adder)
- 加法器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about adder for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
slave_tb
- 实现对slave模块仿真的tb，利用三态始能实现。-verilog slave tb is useful
SPI
- SPI verilog 代码 有代码和TB 以及文件说明-SPI verilog
tb
- 八线译码器的源文件程序用三态门控制其输出输入-entity eightbitcounter
4613m73a_nand_model
- File Descr iptions: --- --- --- nand_model.v -structural wrapper for nand_die_model nand_die_model.v -nand model of a single die nand_defines.vh -file used to generate correct port maps for nand_model instanciation. nand_parameters.vh -fi
random
- 随机数产生以及发牌程序 包括test的tb程序-Random number generator and licensing procedures, including test
six-digit-counter-with-tb
- VHDL source code of six digit counter with testbench,with comments included
ifft
- 基于ise软件的ifft编程,包括tb测试文件-the ifft programming of base on ISE software，include tb test file
Carry_Select_Adder_Verilog
- 进位选择加法器，verilog实现。包含3个TB。-Carry Select Adder. Verilog fulfilled. Three testbenches included.
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
32_by_8_RAM
- 32*8 RAM。Verilog实现。包含TB。-32 by 8 RAM. Testbench included.
randomizervhdl
- Randomizer Vhdl he RTL now is working correctly, and the TB also is working but there is a problem in the sequence of the reset and and the load
VGA_SYNC_TB
- TB file for text VGA_SYNC