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LED七段译码
- 初次上传文件，采用文本格式编辑内容，不知道是否妥当，如有不便之处，敬清各位原谅。-initial upload documents using text format editorial content, I do not know whether they are appropriate, if any inconvenience, King - forgive me.
wavefetch
- ModelSim的波形比较的功能可以将当前仿真与一个参考数据（WLF文件）进行比较，比较的结果可以在波形窗口或者列表窗口中查看，也可以将比较的结果生成一个文本文件-ModelSim waveform can be compared to the current functional simulation with a reference (WLF paper ), the results can be compared in the waveform window or window List
zffsq
- 此文是一个完整的字符发生器的设计及设置,文中有完整的vhdl代码及原理图.-This article is a complete character generator design and installation, a complete text of the code and vhdl diagram.
CPU_16.rar
- vhdl语言的16b cpu代码 全部的代码我会依次上传 另有说明txt文本,VHDL language 16b cpu code all the code I will upload the text otherwise stated txt
FPGA-LCD12864v.rar
- FPGA驱动LCD12864显示，可显示图形和文字，显示内容可根据实际情况而定,FPGA-driven LCD12864 show that can display graphics and text, display content can be determined according to the actual situation
FPGA_PWM_VHDL.rar
- FPGA_EP2C5T144C8电机控制PWM、QUARTUS II 工程文件，非文本文件！可以直接使用！,FPGA_EP2C5T144C8 motor control PWM, QUARTUS II project file, non-text files! Direct access to!
minus
- 一位二进制全减器的设计，分别用原理图输入法和文本输入法，用分层设计的方法完成-A binary full subtractor design, respectively, schematic input and text input method, complete with a hierarchical design method
ISE_lab19
- 俄罗斯方块VHDL实现，。该设计由下面模块组成：键盘输入模块，游戏控制模块，图像显示模块，文字显示模块，存储单元，复用单元和VGA 控制模块组成。其中图像显示模块和文字显示模块复用VGA 控制模块。游戏控制模块，图像显示模块和文字显示模块通过存储单元交换数据。-Tetris VHDL implementation. The design consists of the following modules: Keyboard input module, the game control modul
ddrsdram_verilog
- 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with veri
vhdl_source
- 硬件编写语言，很多VHDL源码例程，纯文本，可直接用在工程中-Hardware language, VHDL source code a lot of routines, plain text, can be directly used in engineering
MAX-PLUSII-soft
- MAX+PLUSII软件是一个功能强大，容易使用的软件包，它可以以图 形方式、文字输入方式（AHDL、VHDL和VERILOG）和波形方式输入设计文 件，可以编译并形成各种能够下装到EPROM和各种ALTERA器件的文件，还可 以进行仿真以检验设计的准确性，下面举例说明该软件的使用-MAX+ PLUSII software is a powerful, easy-to-use software package, which can graphically, text input me
fft1
- a nice text file explaining the fft
lcd_ddram
- 用于控制12832LCD文字显示的源程序，基于状态机制方法统编写的-12832LCD used to control the source text, based on the method of integration mechanisms for the preparation of status of
spreadspectrum1
- these are verilog files but i am uploading in text(notepad) format
xianshi_lcd_0
- 实现了lcd1602显示的功能，可以在lcd上显示“年”字，有利于初学者学习lcd在fpga上显示，采用文本编辑的，利用quartus ii 702-Achieved lcd1602 display function, you can lcd display " " The word will help beginners learn lcd display in the fpga, using a text editor, using quartus ii 702
Text-IO
- 基于VHDL的Testbench读取文件的编写，很有用的 基于VHDL的Testbench读取文件的编写，很有用的-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example
VerilogHDL-literacy-text
- VerilogHDL扫盲文 适合刚刚接触Verilog HDL的同学。生动易懂-VerilogHDL literacy text for students new to Verilog HDL. Lively and easy to understand
synplify_pro-text
- 介绍了synplify pro的使用方法，好不容易找到的，欢迎下载，希望与大家共享。-introuducing the text of synplify pro,it is fit for learning the application of the soft
Text-shaped-LCD
- 文字形LCD Text-shaped LCD #include "HT66F50.h" const unsigned char Table1[] = "Kun" //所要顯示字元 unsigned char DATA_BUS @0x20 //sfr DATA_BUS=0x90 //DATA bus=P1 #define RS PA0 //P35=RS=0指令暫存器，RS=1資料暫存器 #define RW PA1 //P36=RW=1讀取，RW=0寫入
5.-VGA-Text-mode
- A tile-mapped pixel generation scheme is discussed in Section 13.3. A tile can be considered as a super pixel. Whereas a pixel is defined by a 3-bit word in a bit-mapped scheme, a tile is mapped to a predesigned pattern. One method of constructing