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fifoed_avalon_uart9.1_applicaton
- 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
uart
- the uart model is used to design the synthies and beherival model in verilog fpga
UART_Verilog
- Altera FPGA的UART通讯程序-Altera FPGA' s UART communication program
x3cs400_uart
- 基于X3cS400的串口通讯程序，开发环境ISE7.0，使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA， develop enviroment： ISE7.0，completed by verilog。 The result could be seen on the Uart debug assitant.
uart
- RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232
URAT_transmitter_receiver_VHDL
- 基于UART的VHDL程序，包括顶层程序、波特率发生器程序、UART发送器程序、UART接收器程序4部分程序。有详细注释，并在每个程序后附上一张仿真波形图，便于理解和验证。-UART in VHDL-based procedures, including the top-level procedures, procedures for the baud rate generator, UART transmitter program, UART receiver program four par
uart
- 自己写的Verilog写的串口程序，实现收发功能。方法不错，可以参考下。-verilog...uart...
uart1
- RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
RS422_receiver
- UART--异步串行通讯 接收逻辑 （Verilog）16倍时钟接收-verilog--A UART Receiver 16 clock
uart
- it contains pdf file which has vhdl program of uart (universal asynchoronus receiver and transmitter). which very simple and easy to understand
uart_read_send
- uart自收发的vhdl实现,包括quartus工程文件及modelsim仿真工程文件(调试通过)-uart vhdl from the transceiver to achieve, including the quartus project file and modelsim simulation project file (debugged)
uart_verilog
- UART Verilog，书中里的例子，绝对正确，用Verilog语言编写的串口通信例子-UART VerilogCommand Parsing NiosII serial serial parts, including the interruption, send the command prompt, receiving treatment and other characters. Spent a lot of hard work! Definitely useful for beginn
uart
- 基于verilog HDL编写的串口通讯接口uart程序-Prepared based on verilog HDL uart serial communication interface program
uart16750
- UART 16750 source code for VHDL
Mars_EP1C3_S_Core_V2.0
- 此包中为Mars_EP1C3_S_Core_V2.0 FPGA学习板中的接口实验代码.共包括10个实验源代码:7段数码管,i2c,KEYSCAN,MCU,PS2,UART,VGA，蜂鸣器，跑马灯和拨码开关. -This learning package for Mars_EP1C3_S_Core_V2.0 FPGA board interface test code. A total of 10 experiments, including source code: 7 segment di
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
UART
- UART是一种通用串行数据总线，用于异步通信。该总线双向通信，可以实现全双工传输和接收。在嵌入式设计中，UART用来与PC进行通信，包括与监控调试器和其它器件，如EEPROM通信。-UART is a universal serial data bus for asynchronous communication. The two-way communication bus, can achieve full-duplex transmit and receive. In embedded d
uartverilog
- Verilog Uart经典实例，适合初学者练手，建议收藏-Verilog Uart classic example, training for beginners hand, the proposed collection of
RS-232C_UART
- 基于Verilog的RS-232C（UART）接口的设计与实现 -Based on Verilog' s RS-232C (UART) interface, Design and Implementation