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一个简单的UART
- 实现串口基本功能，具有奇偶检验，主时钟与波特率相差16倍(Basic function, a serial port with parity check, master clock and the baud rate is 16 times clk)
RX_IP_Source
- 串口接收ip核，配合 nios 使用，减少cpu资源开支。(uart receive TX_IP_Source)
TX_IP_Source
- 串口发送ip核，配合 nios 使用，减少资源开支。(uart transmit TX_IP_Source)
uart_control
- UART接口的读写，8bit数据位，无停止位(UART interface read and write, 8bit data bits, no stop bit)
07_uart_test
- uart通信协议的Verilog编码实现，以及完整的测试文件。(UART communication protocol Verilog encoding implementation, as well as a complete test file.)
eetop.cn_uart 源码 (Verilog)
- Verilog编写的UART通信模块，比较清晰(UART model wrote by Verilog)
eetop.cn_fifouart_latest.tar
- 用Verilog编写的带FOFI的UART model，比较好(FOFIUART model wrote by Verilog coding)
tx_rx_fifo
- 通过串口将接收到的数据存入fifo,fifo存满后使能串口发送功能，将接收到的数据发送出去(Use fifo to realize the receive and send function of the uart. The function is no problem.)
Uart
- 单片机通过串口接收和发送数据，实现数据可视化(Single chip computer receives and sends data through serial port to realize data visualization)
Uart
- fpga串口通信底层实现程序，可以实现串口的收发工作。(The underlying implementation of FPGA serial communication)
FPGA_UART
- 代码已通过实验测试，实现串口助手在线调试(The serial debug of the serial port of UART is realized through FPGA. The result is very successful after testing.)
urat接收程序
- uart串口接收程序，实现基于Rs232传输线的数据的接收。(UART serial receiving program to realize data receiving based on Rs232 transmission line.)
uart_latest.tar
- UART的VHDL建模代码，是一个标准的IP核(UART's VHDL modeling code is a standard IP core)
test_uart
- 该资料包含用FPGA（EP4CE22F17型号）编写的UART通信程序，最重要的是里面含有串口波特率可调，包括一些常见的波特率。(This information includes UART communication program written by FPGA (EP4CE22F17 model), and most importantly, it contains serial port baud rate tunable, including some common baud rate
07_uart_test
- 利用FPGA的并行方式调试UART，与单片机的调试方式做比较(Using FPGA to debug UART in parallel, make comparison with the way of MCU debugging)
FULL_UART
- UART using FPGA implementation
uart_test_Verilog
- 用verilog实现了uart功能的demo工程。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置即可。(The demo project of UART function is realized with Verilog. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify the pin configura
uart_rx
- UART FPGA串口发送程序，已经调试通过，可以放心使用，谢谢，(Serial transmission program, has been debugged, can be assured to use, thank you)
uart_working_transmit
- UART transmission vhdl code, for nexys 3 fpga board
uart_receiver
- Uart receiver VHDL code