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fanzhen
- 简单使用的UART通信模块，用Verilog编写通过仿真，直接可用-Easy-to-use UART communication module, and the preparation of the adoption of Verilog simulation, directly available
uartverilog
- xilinx提供的verilog_uart源码,适合做串口的人学习-Xilinx provided verilog_uart source, suitable for those who study serial
uart
- 用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.-Achieved using VHDL serial communication procedures, can be synthesized and downloaded to the FPGA to run.
miniuart.tar
- Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost eve
x1Altera_uart_VHDL
- 经典UART程序，通用异步收发器设计的vhdl语言,帮助大家学习UART知识-UART classical procedures, UART VHDL design language, to help everyone study UART knowledge
x2uart-all
- 适用异步收发器设计的vhdl语言,是学习UART知识的好例程-Asynchronous Receiver Transmitter apply VHDL design language, are a good knowledge of study UART routines
x3uart
- 学习UART知识，经典UART程序，通用异步收发器设计的vhdl语言-UART study of knowledge, classical UART procedures, UART VHDL design language
UART0_2
- vlsi UART referene, use UART0_3
rd1042_source_code
- hi this reference code for UART use UAER0_3-hi this is reference code for UART use UAER0_3
337531448051UART
- this UART reference
test_uart
- uart VHDL code : include tx,rx,parity bit control
uartfifo
- FPGA串口代码实现，带串口模块控制程序-Realization of UART in FPGA, with UART module control codes.
UARTCODE
- 一个有关于UART开发的自己的一个VHDL代码-A UART has developed its own about a VHDL code
UART
- Universal async Transmitter Receiver
UARTC
- UART Controller VHDL File
UART_DMA
- 基于ALTERA公司的NIOSII的串口通信DMA传输设计-NIOSII based on ALTERA s DMA transfer of the serial communication design
AVR_UARTFPGA
- 基于VHDL（verilog）语言的UART的设计与实现。全面模仿AVR的UART功能，与AVR直接实现接口调试。资料全面完整。-Based on VHDL (verilog) Language Design and Implementation of UART. UART fully mimic the function of AVR, and AVR debugging interface directly to achieve. Overall integrity of the infor
uart_rxd
- 基于verilog hdl的UART串口接收子程序。-Verilog hdl a UART-based serial port to receive subroutine.
03.EDK8.2
- 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-
Serializer
- Serializer - UART Transmitter and Receiver Complete Project with waveform file-Serializer- UART Transmitter and Receiver Complete Project with waveform file