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clock
- 用verilog语言实现数字时钟，有注释，规范-Digital clock using verilog language, there are notes, specifications
Verilog
- verilog digital clock
clock
- verilog 实现的跑表程序。可以对这个程序加以修改，可是显现电子钟的设计。设计可以根据需要实现分秒。同时可以改成是LED的跑等程序。功能强大的很！-verilog implementation stopwatch program. This procedure can be modified, but the show clock designs. Design can be according to the need to achieve every second. At the same
15NIOSIIclock
- nios num clock verilog code
clock
- 本实验实现一个能显示小时，分钟，秒的数字时钟（贝一特电子）Verilog源码-The experimental realization of a can show hours, minutes, seconds, digital clock (a special e-bay) Verilog source
timer
- 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
paobiao
- 一个用verilog编的时钟程序A clock with the procedures for verilog-A clock with verilog program for A clock with the procedures for verilog
verilog
- 多功能数字时钟的verilog语言描述，基于quarters II平台-Multifunction digital clock verilog language descr iption of quarters II-based platforms
spi
- SPI Verilog code with programmable clock
clock
- verilog HDL 编写的时钟分频器-prepared by the clock divider verilog HDL
clock
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
clock
- verilog program for real time clock.. select the .v file to view the code.
clock
- 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
Downloads
- clock divider in verilog for FPGA use
clock
- verilog hdl代码 实现显示在数码管上显示时间，日期-verilog hdl code to achieve control in the digital display shows time, date. .
6clock
- verilog 电子表。可显示年，月，日，支持闰年。-verilog electronic form. Displays year, month, day and support a leap year.
clock_divider
- clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
clock
- verilog数字钟 Verilog HDL 写的不是很好,有好的就不要下我的了-verilog clock
Verilogexample
- verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci
Clock generator
- A clock Generator in verilog