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video_compression
- 用VHDL实现的视频压缩算法，希望大家学习学习-Using VHDL implementation of video compression algorithms, study study hope that everyone
yuv_rgb
- 完成ITUR656标准的视频流数据向RGB格式的转换。-Complete video streaming ITUR656 standard data format to RGB conversion. Test module
video_control_procedure
- 用VHDL实现视频控制程序(实现对图像的采集和压缩)-Using VHDL video control procedures (the achievement of the image acquisition and compression)
03.EDK8.2
- 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-
4559939-VGA-Video-Signal-Generation
- source code VGA for Xilinx FPGA Spartan 3E
DE2_70_TV
- --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor shoul
vga2
- VHDL code for UP2 board of Altera, that generate a video signal to VGA port.
DE2_LCM_TV_NTSC
- DE2上的基于FPGA视频开发资料第二部分-DE2 video
example1
- 本例程属于独立实验，主要是让大家熟悉一下VHDL 语言基本语法，这是比较简单的 程序了。实现一个将时钟信号clk 十分频的功能，可以通过波形仿真来看效果。 波形仿真的过程可以参考视频“波形仿真.exe”文件，有比较详细的操作方法。其实 在例程的项目中已经包含了波形仿真文件，大家可以直接仿真，观察结果。 -This routine is an independent experiment is designed to allow you familiarize yourself
MAIN_RX_V10
- 8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.
FPGA2
- 华清远见FPGA 第2讲、FPGA设计入门2 视频-Huaqing vision FPGA Part 2, FPGA design entry-2 video
FPGA2-4
- 华清远见视频，FPGA入门视频第二讲第4部分-Huaqing vision video, FPGA Introduction Video Part 4 of the second stress
61EDA_C878
- fpga tv转vga 解码器adv7180，视频转换adv7123-fpga tv to vga，decoder adv7180，video converter adv7123
vhdl
- vhdl 语言的教学视频 很好的教学视频 适合初学者使用-vhdl language teaching video A good teaching video for beginners
d1_dec
- d1(BT.656) video decoder VHDL code
Focusing-system
- 应用FPGA以及VHDL编程语言、视频输入芯片SAA7111和输出芯片SAA7120实现对某固定图像的自动调焦-Application of FPGA and VHDL programming language, video input and output chip SAA7120 SAA7111 chip implementation of a fixed image of the auto-focus
AnEfficientDouble-FilterHardwareArchitectureforH.2
- 在此提出了一種新穎的硬體結構 實時執行的自適應去塊效應 過濾過程中指定的H.264/AVC視頻編碼 標準。-In this paper,a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard, is presented.The deb
ug_vip
- Altera公司原版设计手册，关于video and image processing ip-This document describes the Altera® Video and Image Processing Suite collection of IP cores that ease the development of video and image processing designs. You can use the following IP cores i
fifo
- 一种用于数字视频信号处理的嵌入式FIFO-Signal processing for digital video embedded FIFO