搜索资源列表
usartV1.2
- 基于Verilog实现串口通讯，通过串口调试助手可测试(Serial communication based on Verilog, through the serial debugging assistant can test)
LED_200T
- 本工程包含了一个LED灯测试程序，可以任意更改测试模式。(This project contains a LED lamp test program, you can change the test mode at any time.)
IIC读写EEPROM发送到PC串口
- 能实现用IIC读EEPROM并且将读取的数据通过串口发送到PC端，以及在PC端通过串口发送数据给FPGA，再利用IIC将数据写入EEPROM(The program can realize that FPGA read the data from EEPROM by IIC and then send it to PC by UART,and that PC send the data to FPGA by UART and then write the data to EEPROM by
4LED
- 4LED流水灯程序，可更换频率，采用状态机，低电平有效亮灯，高电平熄灭(4LED water lamp program, you can change the frequency. Using state machine, low level active light, high level extinction)
top1
- 七段数码管译码器，可显示0~9共10个字符。(Seven segment digital decoder, 0~9 can display a total of 10 characters.)
sin
- 能够实现正弦波的输出以及通过频率控制字与相位控制字控制正弦波的相位与频率。(The output of the sine wave can be realized and the phase and frequency of the sine wave can be controlled by two control words.)
参考例程_Verilog例程
- 很多Verilog语言程序可以实现很多的功能。有详细的例程和讲解PDF。(Many Verilog language programs can implement many functions. There are detailed routines and explanations PDF.)
kcsj
- 利用Verilog层次化设计的多功能数字时钟，可以调时，设置闹钟，仿广播台整点报时(The use of Verilog hierarchical design of multi-functional digital clock, you can set the alarm clock, similar to the broadcast station, the whole point of time)
USB2.0的IP核（详细verilog源码和文档）
- USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)
Greedy_snake
- 利用SPARTAN6系列的FPGA，实现开发一款基本贪吃蛇游戏，可在显示屏上游戏，采用verilog代码(Using SPARTAN6 series of FPGA, to achieve the development of a basic snake game can be on the screen game, using verilog code)
ip核
- 购买的beckoff公司的ip核，提供了详细的datasheet以及协议说明，附上调用ip核的文件，采用verilog编写，平台可以在ISE里自己设置(Buy the beckoff company's ip kernel, provides a detailed datasheet and protocol descr iption, attached to the ip kernel file, using verilog prepared, the platform can be set
sdram controller
- Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and t
Digital_Clock
- 用verilog写的数字时钟代码，亲测可用，可自行编写test bench进行仿真(Written in Verilog digital clock code, pro test available, you can write your own test bench for simulation)
SEQ_DETECTOR
- 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data)
VERILOG_HDl
- verilog 初学者常用模块，可作为初学者实验使用(Verilog beginners commonly used modules, can be used as beginners experimental use)
A4_Clock_Top
- 24小时制数字时钟，可自行调节时间，能暂停。(24 hours digital clock, can adjust time, can pause.)
apb
- APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
i2c
- I2C逻辑实现，完整的I2C逻辑功能，可以实现I2C主设备功能(I2C logic implementation, complete I2C logic function, can realize the function of I2C main equipment)
Johnaon_counter
- 本设计为六位约翰逊(Johnson)计数器，首先给大家介绍一下什么是约翰逊计数器，它又称扭环计数器,是一种用n位触发器来表示2n个状态的计数器。它与环形计数器不同,后者用n位触发器仅可表示n个状态。2~n进制计数器(n为触发器的个数)有2~n个状态。若以6位二进制计数器为例,它可表示64个状态。但由于8421码每组代码之间可能有二位或二位以上的二进制代码发生改变,这在计数器中特别是异步计数器中就有可能产生错误的译码信号,从而造成永久性的错误。而约翰逊计数器的状态表中,相邻两组代码只可能有一位二进
unsigned_array_multiplier
- 4X4位的无符号型阵列乘法器，可以提高乘法的运算速度(4X4 bit unsigned array multiplier, can increase the multiplication of the operation speed)