搜索资源列表
CPU-Pipeline
- 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
traffic_light
- 使用Verilog编写交通灯控制代码，能够直接进行运行仿真。(Using Verilog to write traffic light control code, can run the simulation directly.)
dsp
- 程序提供特殊的DSP指令，可以用来快速的实现各种数字信号处理算法。(The program provides special DSP instructions, which can be used to quickly implement various digital signal processing algorithms.)
pipelines
- 将组合逻辑系统地分割，并在各个部分之间插入寄存器，并暂存中间数据的方法。 将一个大操作分解成若干的小操作，每一步小操作的时间较小，所以能提高频率，各小操作能并行执行，所以能提高数据吞吐率。(A method to divide the combined logical system into a register and temporarily store the intermediate data between the parts. A large operation is decomp
timing_constraints
- 方法能够自动地约束 PLL 的输入和输出时钟。ALTPLL megafunction 中指定的所有 PLL 参数都用于约束 PLL 的输入和输出时钟。(Methods can automatically constrain PLL input and output clock.Named in ALTPLL megafunction.All PLL parameters are used to constrain PLL input and output clocks.)
led_test
- 基于Verilog硬件语言的流水灯设计，可以实现4个led灯按照流水灯的形式闪亮。(ased on the flow lamp design of Verilog hardware language, 4 LED lights can be realized in the form of flowing light.)
spi_master
- 用Verilog写的SPI代码，可读可写，刚仿真完，还没上板，尴尬，主要是官方限制不上传就不能下载～～～～～～～～～～～～～～ 下面的英文是百度翻译过来的，鬼畜的我都不知道啥意思～～～～(The SPI code written in Verilog is readable and writable. After the simulation is finished, it is not yet on board. Awkwardly, it is mainly that official r
CAR_LI2
- DE1-SOC实验开发板和Verilog HDL语言的交互式程序作品，选择避障小车作为课程设计题目，并根据选题制定了如下设计需求： 1.能实现基本的避障小车功能，即躲避障碍，变速，计分，计时显示游戏开始、进行和结束画面； 2.能实现人机交互功能，玩家可通过外接键盘或DE1-SOC开发板自带按键和开关操作小车转向； 3.能通过VGA在显示屏中显示，并且能达到5Hz的刷新频率； 4.能实现自定义小车和障碍物皮肤的功能；(DE1-SOC experiment development board
spi_8r8w
- 同时实现多个SPI从设备的连续读写，读写字节数可变化(implement multiply spi slave read/write operation, and the operation's bytes can be changed)
src
- 基于AXI 总线的可配置脉冲计数器，可以配置计算脉冲的个数。(The configurable pulse counter based on AXI bus can be configured to calculate the number of pulses)
C5G_LPDDR2_RTL_Test
- LPDDR2工程，alteral的c5芯片，板子上验证过，可以直接用。(LPDDR2 project, alteral's C5 chip, has been verified on board and can be directly used.)
led_test
- 一个简单的LED跑马灯实验，通过延时来控制LED的闪烁时间，可以通过这个程序来进行verilog语言的入门(A simple LED marquee experiment, through the delay to control the LED flash time, can be used to get the introduction of Verilog language through this program)
at7_ex04
- 通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at rando
pwm
- 本程序可以实现输出不同占空比（0-100）和不同频率的pwm波形；满足驱动不同硬件的需求；(This program can output PWM waveforms with different duty cycles (0-100) and different frequencies, and meet the needs of different hardware drivers.)
C5G_SRAM_RTL_Test
- 官网c5板子的SRAM工程，可以直接一直使用。(The SRAM project of official website C5 board can be used directly)
task1-2
- 通过程序点亮LED灯，程序控制简单，还可以一次做成流水灯(LED lights can be lit by programs, and the program control is simple, and the water lamp can be made at a time.)
car_detect
- 停车场中车辆进出的检测与记录，可得出停车场的车数(The number of vehicles in the parking lot can be obtained by detecting and recording vehicle entry and exit.)
数电开放实验
- 基于Basys2的带测温、定闹钟、温度上下限报警装置的数字电子钟，可自动处理闰年闰月。(Basys2 temperature measurement, alarm clock, temperature alarm device based on digital electronic clock, can automatically handle leap year leap.)
spi_master
- 用verilog编写的SPI代码，这个代码是FPGA作为主机可以发送和读取数据，上板验证过，我测试的时候SPI的CLK速率是5M，读写都没问题，稳，至于更高的速率没测试过。 下面鬼畜的百度翻译大家就不要看了，我不知道他想表达啥意思～(SPI code written in Verilog, the code is FPGA as the host can send and read data, the upper board verified, when I test the SPI CL
Verilog
- 01-08例程为数电基础部分：比较简单，代码中可明显看出或是有中文注释，或是在工程代码主文件最前面有文字注释说明。(The 01-08 routine is the basic part of the digital power: it is relatively simple. It can be clearly seen in the code or have Chinese annotations, or in the front of the master code of the eng