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booth_mul
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multipliers. The multiplier used to impr
sjhsh.rar
- 用FPGA计算三角函数，实现三角函数算法,完成快速三角函数运算,FPGA calculated using trigonometric functions, trigonometric function algorithm to achieve complete fast trigonometric computing
ataninfpga.rar
- 基于FPGA的快速反正切运算实现方法可以用于解调的相位计算,Fast FPGA-based computing arctangent demodulation method can be used to calculate the phase
mul64
- Verilog实现的64位乘法器，该乘法器是我所见过的最牛的乘法器、运算快、资源利用少-Verilog implementation of the 64-bit multiplier, the multiplier is the most I have ever seen cattle multiplier, computing faster, less resource utilization
用VHDL编写的计算器
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算 ,Prepared using VHDL Calculator: able to achieve simple addition and subtraction, multiplication and division 4 computing
MIPS
- 组成原理大作业--基于MIPS的运算器设计，内附详细设计文档，包含设计文档和使用手册，主程序，测试程序，还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条，用Verilog编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and u
cordic
- 用verilog语言实现的cordic算法，计算角度-Use verilog language realization of cordic algorithm, computing Angle
ALU
- vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
s
- 基于VHDL的选择运算器，可以通过选择端选择加减与或四种运算，每个时钟周期刷新结果一次。注释已给出。-The choice of VHDL-based computing device, you can choose by selecting the side addition and subtraction with or four kinds of operations, the results of one per clock cycle refresh. Note has been gi
8-bit
- 最基本的vhdl運算，採用8bit作乘法器，將兩串8bit的值輸入之後進行相乘-VHDL basic computing, the use of 8bit for the multiplier, will be the value of two strings of 8bit input multiplied after
16weiyunsuanqi
- 16位运算器的设计和实现，具有参考价值，适合vhdl课设-16-bit computing design and the realization of a reference value for class-based vhdl
fpga-pulse_sequence
- pulse_sequence.vhd 并行脉冲控制器 light.vhd.vhd 交通脉冲控制器 division1.vhd 电压脉冲控制器中的分频 ad.vhd 电压脉冲控制器中的A/D控制 code.vhd 电压脉冲控制器中的脉冲运算模块 voltage2.bdf 电压脉冲控制系统-pulse_sequence.vhd pulse controller parallel light.vhd.vhd traffic controller division1.vhd puls
OPERATION_UNIT
- 本程序为加密芯片内部加密运算单元部分，包括32位减法器、移位寄存器、加/减法器、寄存器等，对密码芯片运算部分设计具有一定指导意义-The procedure for encryption chip unit internal encryption algorithms, including 32-bit subtraction, and shift register, add/subtraction, and register and so on password-chip design has
alu
- 用VHDL实现8种运算的ALU，带鱼不带符号的加减乘除，与或异或和求反-Use VHDL to achieve the eight kinds of computing ALU, hairtail unsigned addition and subtraction, multiplication and division, with or XOR and seek anti-
altera_Sine_CosineusingtheCORDICalgorithm
- 计算机算术是微处理器运算的数学基础,其中一个非常重要的部分就是超越函数的计算问题。数学函数的VHDL实现-Computer arithmetic is a microprocessor based on mathematical computing, in which a very important part is the calculation of transcendental function. VHDL realization of mathematical functions
ALU
- 在Xilinx7.1平台下编写的ALU代码，可以实现五位加法、减法、与、异或四种运算！-Xilinx7.1 platform in the preparation of the ALU code, can be achieved five adder, subtraction, and, four computing XOR!
disanci
- 5位的操作数X和Y输入后暂存在寄存器A和B中，两位的操作控制码control暂存在寄存器C中，按照control码的不同，分布实现下列操作： 00控制X+Y 01控制X-Y 10控制X and Y 11控制 X xor Y 运算结果暂存在寄存器D中，然后输出。 -5 of the operand X and Y after the temporary importation of A and B in the register, the two operational c
logic
- 5位的操作数X和Y输入后暂存在寄存器A和B中，两位的操作控制码control暂存在寄存器C中，按照control码的不同，分布实现下列操作： 00控制X+Y 01控制X-Y 10控制X and Y 11控制 X xor Y 运算结果暂存在寄存器D中，然后输出。 -5 of the operand X and Y after the temporary importation of A and B in the register, the two operational c
61EDA_D1051
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
reconfigurable-computing
- 面向图像处理的可重构计算系统结构 大连理工大学硕士论文 -For image processing reconfigurable computing architecture master' s thesis, Dalian University of Technology