搜索资源列表
verilog SDRAM core
- 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
MC8051 IP Core
- 8051的IP软核，使用硬件描述语言编写，可以下载到FPGA/CPLD中作为片上系统的处理器-8051 IP soft-core, the use of hardware descr iption language can be downloaded to the FPGA / CPLD as a system-on-chip processor
USB 2.0 IP Core
- USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
Altera-AHDL语言设计的PCI总线Core
- Altera AHDL语言设计的PCI总线Core,很难得的PCI设计资料-Altera AHDL design Core PCI, the PCI is difficult to design information
PS2-IP-CORE-VHDL
- 一个PS2 IP CORE(VHDL) for FPGA
uart.core.for.FPGA
- 一个UART的FPGA core，附有详细的代码阅读笔记
USB 1.1 IP-CORE和设计范例 VHDL源代码
- USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
IP core
- VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
Free ARM-7 Core (Verilog) 可跑 uClinux
- 一个 Free 的 ARM-7 Core,是使用 Verilog 编成,综合后占用资源小,可以执行 uClinux 等程序或系统,内附详细说明的 PDF 档及源码 Verilog 编程等.
USB.rar
- 用VHDL实现的USB IP核，大家可以参考下,Use VHDL to achieve USB IP core, we can refer to the following
usb11.rar
- 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。,Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
USB2.0IP.rar
- 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档,Complete Verilog language developed by USB2.0 IP core source code, including documentation
Altera_8051_IPcore_v1.2.rar
- Alera 的8051 IP core的示例文件5个,Alera the 8051 IP core of the sample file 5
SPI_verilog_vhdl.rar
- SPI串口的内核实现（分别使用verilog和vhdl语言描述的）,The core of the realization of SPI serial port (using Verilog and VHDL language descr iption of the)
can.rar
- can IP CORE .VERY GOOD AS A STUDY FILE,can IP CORE. VERY GOOD AS A STUDY FILE
vhdl-arm-core
- 用vhdl语言实现arm内核，压缩包中有19个代码共同组成这个arm内核，程序比较大，应用时要注意那个代码是顶层实体。用quartus2软件即可打开仿真。-Vhdl language used arm core, compressed package code of 19 common core component of this arm, procedures, and application code should be noted that top-level entity. Used t
Intel-Core-i3-i5-i7
- Intel Core i3，i5，i7.rar-Intel Core i3, i5, i7.rar
ethernet10-100M-IP-core
- 以太网10-100M IP核Verilog源码，可综合-Ethernet 10-100M IP core Verilog source code can be integrated
vhdl-fft-core
- FFT ip core，fft信号处理模块， VHDL语言编写-FFT ip core
alize-core-master
- alize core-master source codes