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ALU1
- ALU 指令格式(16位） op DR SR fun 0--3 4—7 8--11 12--15 指令类 OP码 指令 FUN 功能描述 控制 0000 NOP 0000 空指令 HLT 0001 停机 有条件跳转 0010 JZ 0000 Z=1，跳转 JC 0001 C=1，跳转 JNC 0010 C=0，跳转 JNZ 0100 Z=0，跳转 Jump 0101 无条件跳转 LOAD 001
dec.vhd
- vhdl code for a 16 bit decoder design
Morgan.Kaufmann.VHDL.2008.Just.the.New.Stuff.Dec.
- A tutorial e-book fo VHDL by Kaufma-A tutorial e-book fo VHDL by Kaufmann
dec
- A Dec example written in VHDL.
FirDec
- 用FPGA实现FIR抽取器源程序，用于数字下变频。-A program to realize FIR DEC.
dct
- all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
BCH-dec
- 基于C的BCH纠错码研究，已经做了调试，和你好用。-C-based study of the BCH error correction code, debugging has been done, and Hello to use.
8051_hex_dec_conv
- 8051 Assembler. hex to dec conversions.
dec
- sumador en vhdl, plataforma xilinx
bch_dec
- BCH编解码 Features : – allows to correct up to 2 errors. – supports 16/32/64/128 bit memories (typical memory word sizes). – operates on complete memory words in a single cycle. – pure combinational logic design-The double error correcting (DE
Counter_Debounce
- Verilog 3-bit Inc/Dec Counter on Spartan3E
dec
- verilog code for decoder