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vhdl_clock
- VHDL实现数字时钟，利用数码管和CPLD 设计的计数器实现一个数字时钟，可以显示小时，分钟，秒。程序主要要靠考虑十进制和六十进制计数器的编写。 以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends
chufaqi
- 时序电路是指它的输出不仅取决于当时的输入，而且也取决于过去的输入，即过去输入不同，则在当前的情况下，输出也可能不同。-Sequential circuit is the output depends not only on its input at that time, but also on past input, that is different from the last input, then in the current circumstances, the output also
digitalwatch
- Describe: This VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The e
Bandwidth_kmeans
- The Video Content Analysis Homepage was established in 1999 to provide a central location for information and resources related to video/audio content analysis research. The emphasis of the Video Content Analysis Homepage is on research rather than o
FSM
- 用程序实现状态机功能，有限状态机是指输出取决于过去输入部分和当前输入部分的时序逻辑电路。一般来说，除了输入部分和输出部分外，有限状态机还含有一组具有“记忆”功能的寄存器，这些寄存器的功能是记忆有限状态机的内部状态，它们常被称为状态寄存器。在有限状态机中，状态寄存器的的下一个状态不仅与输入信号有关，而且还与该寄存器的当前状态有关，因此有限状态机又可以认为是组合逻辑和寄存器逻辑的一种组合。其中，寄存器逻辑的功能是存储有限状态机的内部状态；而组合逻辑有可以分为次态逻辑和输出逻辑两部分，次态逻辑的功能
IIC-VHDL
- iic 总线在设计时要看你所使用的器件的传输或接收时序 只要会一个，其他的都一样 以下是我在一本书上看到的，感觉很不错，你看看就会用了 -as long as the will a the iic bus depends on the devices you use in the design of the transmission or reception of timing, other-like following, I saw in a book, I feel very g
add
- The circuit 1 in is a 1-bit binary adder with 3 inputs (A, B and Carry-In) and 2 outputs (Sum and Carry-Out).The circuit 2 depends on circuit 1 which create a VHDL file ADD4 which is a 4-bit binary adder built using ADD1 components.