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laboratory-10
- 基于DE2开发板的实例10进行编写,为整个工程的打包文件-this is a file for lab10 of DE2,you can use this to learn how to design a processor
SYNTHPIC.ZIP
- The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the licen
Lab_4_PicoBlaze
- Integrating a picoblaze processor in LabVIEW FPGA by use of CLIP node. Create LabVIEW FPGA Project for Xilinx Spartan 3E starter board. use pBlazIDE to program a psm file that will run on the picoblaze softcore processor.
Avt3S400A_Eval_MicroBlaze_v10_1_03
- Creating Your First MicroBlaze Design with the Spartan-3A Evaluation Kit This tutorial shows how to make use of XPS, BSB, and an XBD file to create and use a MicroBlaze soft processor system for the Avnet Spartan-3A Evaluation Kit.
SinglecycleCPU
- 用Verilog实现一个简单的单周期CPU,并运行Quicksort程序以验证正确性。-This file is written in Verilog to achieve a single cycle processor. It can run in Quartus2.
cpu
- This file is desgined for recinfigurable processor
pyball
- Hex type memory file. Used to update memory in a simple MIPS processor
processor
- 文件中包含一个简单MIIPS CPU的Verilog源代码-File contains a simple MIIPS CPU in Verilog source code
SRAM_1wait
- The aim of this vhdl file is to create a simple interface betwhen the sram and a basic processor on a semisync data bus. This was made using the test board DE2 from Altera.
MIPS_Project
- Verilog Source File. MIPS Processor Pipelining
VGA_CCD531
- 本文围绕一个包含Nios II软核处理器的可编程片上系统展开数码相机的样机设计。论文首先对样机所要达到的整体功能进行了规划,接下来并行开展了软硬件设计。在硬件方面,充分利用了所使用平台提供的SD卡插槽、键盘、数码管、SRAM等各种硬件资源,并用Verilog HDL硬件描述语言设计了样机系统所需要的VGA接口控制器、CMOS图像传感器接口控制器以及VGA显示存储器;在软件方面,本文基于Nios II软核处理器用C语言实现了SD卡的驱动、FAT文件系统的移植、VGA显视器的驱动以及BMP图片文件的
MIPS-CPU
- 完整的32位MIPS处理器工程,拥有整个工程和doc文件说明-Full 32-bit MIPS processor works with the entire project and doc file descr iption
myfpga
- 详细描述设计过程 ① 指令格式设计 ② 微操作的定义 ③ 节拍的划分 ④ 处理器详细结构设计框图及功能描述(评分重点) a. 模块之间的连线单线用细线,2根及以上用粗线并标出根数及. b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上 ⑤ 各功能模块结构设计框图及功能描述(评分重点) ⑥ VHDL代码、UCF文件、测试指令序列(每条指令的含义) ⑦ 实验总结,在调试和下载过程中遇到的问题 -Design Pr
lab6
- 详细描述设计过程和实验中遇到的问题,包括: ① 指令格式设计 ② 微操作的定义 ③ 节拍的划分 ④ 处理器详细结构设计框图及功能描述(评分重点) a. 模块之间的连线单线用细线,2根及以上用粗线并标出根数及. b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上 ⑤ 各功能模块结构设计框图及功能描述(评分重点) ⑥ VHDL代码、UCF文件、测试指令序列(每条指令的含义) 实验总结,在调试和下载过程中遇到的问题