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fir_using_FPGA
- 基于verilog的fir滤波，并带matlab仿真
fir
- 利用FPGA中verlog HDL实现FIR滤波功能,可自行设置相关参数，生成模块-Verlog HDL in the use of FPGA realization of FIR filtering, the provision of the relevant parameters can generate module
65filter
- 65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加 然后相乘得过程-65 FIR digital filter design ~ ~ with simulation data to come in through the importation of data from experiments completed filtering of the digital filter in the whole alg
fir_liujiao
- 利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter
fir
- Verilog编的fir滤波器，可以自己输入参数序列，产生滤波波形-Verilog compiled fir filter, input parameters can be their own sequence, resulting in filtered waveforms
FIRforVHDL
- 17阶的简易低通滤波（FIR），用quartusII 实现（含实验报告）-17 Order of the simple low-pass filter (FIR), with quartusII implementation (including test report)
FIR
- 实现FIR滤波，利用Verilog语言对其进行了设计 -FIR filter implementation using Verilog language design was carried out
fir_asm
- FIR滤波器设计 可以对输入信号进行FIR滤波 看到结果-FIR filter design FIR filter on the input signal to see results
FPGA-FIR
- FIR滤波器，算法，采用VHDL编程语言，算法比较简单，希望对大家有所帮助。-FIR filter algorithm, using VHDL programming language, the algorithm is simple, we want to help.
ADC_DSP_FIR_Filter
- 改程序实现了通过dspic30f5015内部ADC模块对模拟量进行采集，之经过FIR滤波，-Reform program implemented by the internal ADC module dspic30f5015 analog acquisition, the after FIR filtering,
FIR
- 程序对规律的正弦输入和随机的输入进行相同的166阶FIR滤波。输出滤波后结果。-Program of regular sinusoidal input and random input for the same 166-order FIR filter. Output filtered result.
firfilter
- fir滤波 基于fpga 的 三阶滤波-fir filter third-order filter on fpga
fir
- 串行乘法累加结构的FIR滤波器电路，FIR的滤波过程就是一个信号逐级延迟的过程-Serial multiply-accumulate structure of the FIR filter circuit, the FIR filtering process is a signal to the process step by step delay
signal-fir
- FPGA实现FIR滤波器，对信号的滤波处理，其中I用IP核实现数据的存储核-Based on the IP core of FPG, realize FIR filter design
ADS830
- 幅频均衡数字滤波器设计，ad830输入，800阶的FIR滤波，采用电阻网络DA输出，效果很好-Amplitude-frequency equalization of digital filter design, ad830 input, 800 order of FIR filter, using DA output resistance network, the effect is very good
fir
- 基于FPGA的低通滤波器的设计，仿真环境是QuartusII9.0。对信号进行低通滤波，编程成功。希望对大家有所帮助-FPGA-based low-pass filter design, the simulation environment QuartusII9.0. The signal is low-pass filtering, the programming was successful. We hope to help
fir
- 该程序实现了一个FIR滤波加速器，该程序在FPGA板上开发，通过使用VHDL语言来定义RS232端口的使用-design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language.
AD_DF_DA
- FIR滤波代码，先是AD的控制，后面是滤波的代码，系数通过matlab生成-FIR filter
Low-Power-FIR-Filter
- FIR滤波在数字信号领域中很大作用。这个源码很大帮助VHDL工程师或学习者。里面包含说明书。-This report investigates the power consumption of digital arithmetic circuits for use in the design and implementation of a 15-tap programmable Finite Impulse Response (FIR) filter.
FIR设计实现sgh
- FIR滤波FPGA实现 ，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)