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一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
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是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除,Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
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该pdf 详细的介绍了 浮点小数的计算法则，和在vhdl程序中 浮点小数的表示方法，和乘除法的运用
希望对大家有用,The pdf in detail the calculation of the decimal floating-point rules, and procedures in vhdl decimal floating-point method, and the use of multiplication and division for all of us hope tha
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介绍一组浮点数的运算代码，包括加减乘除运算的VHDL代码实现-Introduced a set of floating-point code of the operation, including addition and subtraction multiplication and division operations to achieve the VHDL code
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一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
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一种用VHDL语言描述的浮点除前规格化的源代码编程-VHDL language used to describe a floating-point addition to the source code before the standardized programming
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一种用VHDL语言描述的浮点平方根前规格化的源代码编程-VHDL language used to describe a floating-point square root of the source code before the standardized programming
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VHDl在FPGA上实现浮点运算，给初学者使用-VHDL in FPGA to achieve floating-point operations for beginners
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这是一个用FPGA控制PS2接口的程序，里面用VHDL语言编写，希望大家踊跃下载！-This is a PS2 interface with FPGA control procedures, which use VHDL language, hope that we enthusiastically download!
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基于VHDL语言的32位单精度的浮点加法器-floating point adder based on VHDL
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基于FPGA单精度浮点除法器的实现，有一些源代码，仅供参考。-FPGA-based single-precision floating-point divider realization, there are some source code, for reference purposes only.
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高精度的浮点数除法运算，基于浮点运算的FPGA实现，单精度浮点数-High-precision floating-point division operation, the FPGA based on the realization of floating-point operations, single precision floating point
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该代码描述了一个浮点加法器的功能，浮点格式采用IEEE标准-The code describes a floating-point adder function, the use of IEEE standard floating-point format
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Floating point multiplier
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Floating Point Multiplier in VHDL
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VHDL语言，有符号定点数转化为浮点数，Pavle Belanovic教授编写-Conversion from signed fixed-point to floating-point representation
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这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
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浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
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floating point adder mul and sub in verilog code
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code for fixed & floating point-code for fixed & floating point........
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