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PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
float_mul_verilog
- 浮点乘法verilog代码，浮点格式遵循 IEEE754 标准。-Float Point Multiply , im verilog
bcd2bin_n
- This decoder binary to Binary Coded Decimal. Im tested on s3e-This is decoder binary to Binary Coded Decimal. Im tested on s3e
Hamming_decoder-1
- this program does something im not sure what but all i want is to get into the damn site thank you
AN123
- AMBA Application Note: AN123 - Logic Tile IT1 GPIO example design. -Application note AN123 provides all of the AHB slave features of AN119 with the addition of five 32bit AHB GPIO slaves. The GPIO interfaces are used to configure and test an IT1
AN136
- AMBA Application Note: AN136 - Using Core Tiles stand-alone. -AMBA Application Note: AN136- Using Core Tiles stand-alone. This example design shows how to use Core Tiles as individual units powered through an IM-LT1. A Logic Tile is also requi
AN128
- AMBA Application Note: AN128 - Logic Tile Flashing LED design. -AMBA Application Note: AN128- Logic Tile Flashing LED design. Application note AN128 is a simple flashing LED example design to demonstrate the process of creating FPGA images
UART
- IM DESINING VHDL COD EIN IS THIS CODE IS GOD AND TESTIN VERY GOOD
fp-im-of
- its abt in vhdl ,frequency estiator