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  1. jkandTflipflop

    0下载:
  2. this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for e
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-26
    • 文件大小:82611
    • 提供者:jatab
  1. encoderdecoder

    0下载:
  2. this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year proj
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:142088
    • 提供者:jatab
  1. multiplexersemultiplexer

    0下载:
  2. this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be us
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:90783
    • 提供者:jatab
  1. srandDflipflop

    0下载:
  2. this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for e
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-25
    • 文件大小:205368
    • 提供者:jatab
  1. addersandsubtractors

    0下载:
  2. this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code c
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-27
    • 文件大小:65581
    • 提供者:jatab
  1. binary to gray and gray to binary code converter

    0下载:
  2. this project is based on 4bit binary to gray and gray to binary code converter using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be
  3. 所属分类:VHDL编程

    • 发布日期:2013-10-16
    • 文件大小:60938
    • 提供者:jatab
  1. PROCEDURETOWORKINISE

    0下载:
  2. Procedure to Work in VHDL... by Ashok Kumar . A . M Zebros India
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-13
    • 文件大小:3489881
    • 提供者:Ashok
  1. BASICVHDLCODES

    0下载:
  2. BASIC VHDL DOCUMENTS BY ASHOK KUMAR.A.M ZEBROS INDIA
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:9684
    • 提供者:Ashok
  1. 8-Bit-Up-Counter-With-Load

    0下载:
  2. 8位计数器与负荷 -----------------------8位计数器与负荷 -8-Bit Up Counter With Load 1------------------------------------------------------- 2-- Design Name : up_counter_load 3-- File Name : up_counter_load.vhd 4-- Function : Up counter
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-14
    • 文件大小:4838
    • 提供者:王浩
  1. 4_Low_Power_High_Performance_SRAM_Design_Using_VH

    0下载:
  2. Low Power High Performance SRAM Design Using VHDL By Mahendra Kumar, Kailash Chandra
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-26
    • 文件大小:395909
    • 提供者:shankar
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