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Modelsim_timing_simulation_library
- 文章论述如何将向modelsim中添加仿真库，包括添加xilinx,altera,actel公司的仿真库的方法
altera_ram
- 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。
Altera Modesim破解版的LICENCE
- Altera Modesim破解版的LICENCE. 下载解压后: 1.直接运行mentorkg.exe(生成的license.txt拷贝到D:\altera\80\modelsim_ae\下或者mentorkg.exe拷贝到此目录下运行). 2.设置环境变量lm_license_file="D:\altera\80\modelsim_ae\license.txt" 3.搞定,Altera Modesim cracked version of the LICENCE.
crack-81
- 最新QuartusII8.1的补丁，安装它的破解器，可以获得长期使用权-QuartusII8.1 the latest patch, install it to break, and access to long-term use rights
source
- ModelSim对Altera设计进行功能仿真的简单操作步骤-modelsim simulation
modelsim-using-guide
- modelsim Altera 5.3的使用教程，适合初学者了解第三方仿真工具。-handbook for modelsim Altera 5.3.It is helpful for learning FPGA.
Example-b4-1
- Altera基本宏功能的产生和实现方法.定制一个双端口RAM，DualPortRAM,Quartus II仿真器中做门级仿真,在ModelSim中对这个工程进行RTL级仿真.-Altera basic macro functionality of the generation and realization. Customize a dual-port RAM, DualPortRAM, Quartus II simulator to do gate level simulation, on t
Altera_FPGA_develop(QuartusII_7.2_ModelSim_6.5).ra
- Altera FPGA开发说明（QuartusII 7.2 & ModelSim 6.5）.pdf 建立和编译QII项目 modelsim功能仿真 QII引脚分配 modelsim时序仿真（建立Altera仿真库） QII下载 -Altera FPGA Development Descr iption (QuartusII 7.2 & ModelSim 6.5). Pdf project to establish and build QII QII pin ass
modelsim-ALTERA-manual
- 经常的modelsim使用手册，和Altera公司的FPGA软件配套使用-Regular modelsim manual, and Altera' s FPGA software supporting the use of
ModelSim-Altera61g_CRACK
- modelsim 6.2破解,对于ALTERA 器件-MODELSIM 6.2 CRAK FOR ALTORAL CHIP
Modelsim-functional-simulation
- 介绍了Model Technology 公司的Modelsim XE II v5.6e的主要结构、属性设置、Modelsim XE II v5.6e与ISE5.2的软件接口，测试激励文件的建立以及Modelsim仿真分析方法。Altera公司QuartusII3.0仿真器(Simulator) 的主要结构、属性设置以及仿真分析方法。 -Introduced the Model Technology Modelsim XE II v5.6e company' s main struct
Chapter-2
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-3
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-4
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-5
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-6
- 练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
Chapter-7
- 练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are program
Chapter-8
- 练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
FPGA_CRC
- 用Quartus II 13.0 (32-bit)实现并行计算8位数据宽度的CRC16-CCITT循环冗余码，verilog HDL源代码，并有本人手工计算的原理。本程序已经过ModelSim-Altera模拟，仿真波形文件都在本文件内。-Calculated using the Quartus II 13.0 (32-bit) parallel 8-bit data width CRC16-CCITT cyclic redundancy code, verilog HDL source cod
ModelSim-Settings
- 设置ModelSim仿真步骤,运用Quartus II 13.0 (32-bit) University Program VWF 波形文件编程功能后，使用ModelSim-Altera进行仿真。-Set ModelSim simulation steps, using Quartus II 13.0 (32-bit) University Program VWF programming function waveform file, use the ModelSim-Altera simulat