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ofdm_sch
- GPRS是通用分组无线业务(General Packet Radio Service)的简称，它突破了GSM网只能提供电路交换的思维方式，只通过增加相应的功能实体和对现有的基站系统进行部分改造来实现分组交换，这种改造的投入相对来说并不大，但得到的用户数据速率却相当可观。本实例教授大家GPRS基础知识。
pwm-c
- 用VHDL编写的PWM控制程序，通过寄存器控制20余路PWM输出；qar是quartus的压缩包格式-VHDL prepared using PWM control procedures, through the registers to control more than 20 road PWM output qar is Quartus compressed packet format
MPEG-2_TS
- MPEG2中的TS流！讲解怎么用控制信息代替空包！-MPEG2 in TS stream! Explain how to use control information in place of empty packet!
FPGA_Code_and_training_materials
- 压缩包内包含了：FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！-Compressed packet contains: FPGA design of the primary classes and training classes improve classroom PPT experiment' s source code experimental guide book!
CPU_Architecture
- Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common netw
traffic
- verilog编写的一个交通灯程序，利用状态机实现。压缩包内有说明文档，源代码及时序截图-verilog prepared a program of traffic lights, the use of state machine to achieve. Compressed packet, there are documentation, source code and timing Screenshots
Mars-EP1C6-F_code2
- 此包为FPGA学习板接口实验程序源代码,共包括13个实验程序,有7段数码管,1602液晶显示,12864液晶显示,I2C总线,串口通信,拨码开关等.-The packet interface to FPGA board experimental procedure to study the source code, a total of 13 experimental procedure, there are 7-segment digital tube, 1602 LCD 12864 LCD,
Mars-EP1C6-F_code3
- 此包为FPGA学习板的综合实验程序源代码,包括两个实验:交通灯和数字时钟.-This packet FPGA board to study a comprehensive experimental program source code, including two experiments: the traffic lights and digital clock.
ml510_bsb1_std_ip_ppc440
- 这是Xilinx公司FPGA的标准的基于PowerPC440的IP包底层驱动程序，标准的，很难得。-This is the standard Xilinx, FPGA-based IP packet PowerPC440 the underlying drivers, standard, hard to come by.
l34_parser
- 报文解析，用来判断是否为正常报文及报文分类-Packet analysis, to determine whether a normal packet and packet classification
smii_latest.tar
- SMII接口的mac控制器，通过测试。使用verilog语言！-The Serial Media Independent Interface, SMMI, is a low pin count version of the MII normally used between ethernet MAC and PHY. The Serial Media Independent Interface (SMII) is designed to satisfy the following r
pes2es_top
- 基于MPEG2的视频解复用的设计，正确的分析PES包，得到音视频的基本流。该模块效率很高。-The module is mainly used for synchronous detection MEPGII TS stream. When detected in three consecutive TS packets simultaneously, the output of a sync signal, in which the sync signal driven, TS packet
verilog
- 题目在压缩包中,如：设计4 位超前进位加法器。并给出测试模块和测试分析结 果。 -topic in the packet
System_Demons
- 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实
hamming-code
- 含有四个模块，分别是（1）16位序列产生与分组模块 （2）编码模块 （3）加错模块 （4）译码与分组串行 -Contains four modules, namely (1) 16 sequence generation and grouping module (2) encoding module (3) wrong module (4) decoding and packet serial
Code
- 带丢包的线性均方最小方方差滤波器，这是在经典的kalman滤波器基础上修改的-LMMSE for systems with packet dropouts
ingress
- Verilog 实现1588协议的报文解析功能-Verilog 1588 packet analysis function
VHDL_LAPS
- 简化LAPS协议，对发送的数据包进行封装、传输和接收，，包含FCS是对整个LAPS帧进行CRC校验。-Simplify LAPS protocol, encapsulation, transmission, and receiving the transmitted data packet, containing FCS is performed on the entire LAPS frame CRC.
51_eth_tx_rx
- 51单片机与以太网控制器的设计，实现数据于主机和PHY的封包解包与传输-51 MCU and the design of Ethernet controller, data from the host and the PHY packet unpacking and transmission
14-FPGA-examples
- 14个FPGA例程包，如用FPGA实现跑马灯。多路选择器等-14 FPGA routines packet, such as using FPGA Marquee. Multiple selector