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parallel_to_serial.rar
- 一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据,A parallel to serial verilog source code you can transfer your parallel data to serial data.you have 12bits parallel data then you will have a serial data
CRC
- 这个是我花了一个星期的CRC算法，有并行与串行的区别与时序的分析。。。。希望站长能够同意-This is a week I spent the CRC algorithm, there is the difference between parallel and serial and timing analysis. . . . Hope that regulators can not agree
fir_parall
- 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
mux_reg
- VHDL code for a multiplexer and a parallel/serial in parallel/serial out shift register
LPT_Parallel_Receiver_Alon_and_Julia_Final
- A project in VHDL for Parallel Receiver
parallel-fifo
- 利用Verilog语言编写的并行数据传输程序，在编译环境中编译通过。- the model of parallel data transmit which is written of verilog.
code
- This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
seriall2parallel
- its code for converting serial to parallel processing data
verilog
- 介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作，又可完成子字并行操作模式，即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit* 64bit multiplication operation
parallel-output-controller-(POC)
- 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid
PARALLEL-MULTIPLIER
- vhdl code for a 32 bit parallel multiplier
Parallel-Cable-IV-Guide
- parallel cable 4 datasheet
parallel
- 用VHDL语言实现8255功能，是CPLD比较好的例程-8255 parallel port board with VHDL implementation is relatively good routine CPLD
parallel-to-serial-conversion
- 该模块实现的是并串转换功能，经过仿真验证没有问题-This module is designed to implement parallel to serial conversion
CRC-Parallel-Computation
- 用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based
Parallel-to-Serial
- Parallel interface to serial interface -Parallel interface to serial interface
Eight-parallel-adder
- 8 位并行加法器 vhdl 语言描述-Eight parallel adder
Eight-parallel-by-skulls
- 8 位并行乘法器 vhdl语言描述-Eight parallel by skulls
16-parallel-multiplier
- 简单16位并行乘法器的Verilog程序-16 parallel multiplier Verilog program
32-bit-parallel-interger-bit-
- 32 bit parallel integer bit