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自动打铃系统
- 自动打铃系统，在ＭＡＸＰＬＵＳ平台下动行，能实现计时、打铃控制等功能。 -automatic bell system, the Converter Platform animal, able to plan, a Bell controls.
110detector_lab
- 一个简单的探测110三位的探测器，用逻辑图和vhdl描述，包括实验报告和测试图。-a simple survey of 110 three detectors, and a logical map vhdl descr iption, including reports and experimental test plan.
dct.rar
- 离散余弦变换的设计源代码以及测试源代码和仿真图,Design of discrete cosine transform source code and test source code and simulation plan
ActelFPGA_MSP_ApplicationNote
- 多串口扩展芯片广泛应用于各种多路通信、数据采集场合，它弥补了一般 MCU串口数 量少的不足，扩展了处理器的串口通道，使得处理器能与更多的串口设备进行通信。本方案 采用 Actel Flash 架构的 FPGA 实现扩展多路串口功能，并通过 FPGA 灵活的结构来为用户 定制不同的功能，可以广泛应用于工业控制、智能家居以及其他需要多路串口的场合，该方 案已经被多家公司采纳。 -Multi-serial port expansion chip is widely applied in
cycloneiii
- cycloneiii引脚分配图 excel版本-cycloneiii pin assignment plan excel version of the
Taximeterproceduresandsimulationwithvhdl
- 出租车计价器VHDL程序与仿真。程序最后包括了程序仿真图和出租计价器程序仿真图。-Taximeter procedures and simulation of VHDL. Finally simulation program includes the program plan and rental pricing program simulation diagram.
plan
- using the VHDL, 8bit cpu plan
alu
- 运算器实现，运用Veriolog语言，编程实现，无错误，顺利编译，可执行，仿真图正确~-ALU implementation, the use of Veriolog language, programming, error-free, smooth build, executable, simulation plan correctly ~
altera_up_sd_card_avalon_interface
- altera公司面向大学的大学计划中sd的ip核源程序，-altera company plan for universities in the ip sd_card nuclear source,
pinlvji
- 基于vhdl的等精度数字频率计，经验证，很好用-Based on VHDL precision digital frequency plan etc
Frequency-meter
- 用FPGA实现数字频率计，有数字显示功能-With FPGA realizing digital frequency plan, a digital display function
VHDL-
- VHDL的学习方案 过程 学习指导 实验方案-VHDL study plan process learning guidance
TSMC130
- 本文档提供重要信息，并通知有关此版本的PDK的。谁想要或计划使用的PDK的用户，应先阅读整份文件。-This document gives important information and notice regarding this release of PDK. Users who want or plan to use this PDK should read the entire document first.
ll
- 电子计数器测频有两种方式：一是直接测频法，即在一定闸门时间内测量被测信号的脉冲个数；二是间接测频法，如周期测频法。直接测频法适用于高频信号的频率测量，间接测频法适用于低频信号的频率测量。本文阐述了用数字电路设计了一个简单的数字频率计的过程。-Electronic counter measuring frequency in two ways: one is the direct frequency measurement method, that is, in a certain gate ti
89
- 几种verilog语言的分频计设计，初学者适用-Several verilog language points frequency plan design, for beginners
DF_counter
- 计数式数字频率计，10Hz-10MHz以KHz为单位显示，六位数码管显示，有小数点及溢出标识，1s、0.1s、0.01s闸门时间可选-Count type digital frequency plan, 10 Hz-10 MHz to KHz for unit shows, six digital tube, showed a decimal point and overflow logo, 1 s, 0.1 s, 0.01 s gate time can be chosen
plj_a
- FPGA经典频率计，使用完整的VHDL语言，有足够的注释，一看就会-FPGA classic frequency plan, use the complete VHDL language, have enough comments, a look at will
project9_freq_counter
- 数字频率计的设计,基于VERILOG的数字频率计的设计-Digital frequency plan design, based on the number of VERILOG frequency meter design
A3_OCMJ_good
- OCMJ工程，包括两种写法。VHDL语言，配合使用达盛科技大学计划的开发板。硬件验证成功。-OCMJ projects, including two written. VHDL language, with up to Sheng University of Science and Technology Plan development board. Hardware verification successful.
PLD_design
- Altera大学生计划DE2-115开发板： Nios2开发应用-Altera Students plan DE2-115 board: Nios2 development and application