搜索资源列表
cpld_spi
- cpld spi ，功能基本上满足普通项目的使用，欢迎使用。-cpld spi, function essentially to meet the general project use, Welcome.
MIPS_CPU
- 一个完整的MIPS CPU的设计，是创新设计项目，内含详细的项目设计报告-A complete MIPS CPU design, innovative design projects, detailed project design report containing
stopwatch
- 此程序实现计时秒表功能，时钟显示范围00.00～99.99秒，分辨度:0.01秒 采用PIC16F877单片机，6位数码管显示 开发平台：MPLAB IDE v8.30 类型：工程文件（内有C源码），已验证通过-This program achieved stopwatch function, clock display range 00.00 to 99.99 seconds Resolution: 0.01 seconds using PIC16F877 microcontro
CORDIC_SINE
- xilinx的ISE工程，用CORDIC算法做DDS生成正弦波-xilinx the ISE project to do with the CORDIC algorithm generates sine DDS
13_lcd
- verilog 实现 1602 液晶显示程序。 -a lcd project.It turns out good!
EDA
- EDA实验序列信号检测器和模可变计数器，工程文件和VHDL文件-EDA test sequence signal detector and variable-counter model, project files and VHDL files
20100629001
- 基于NetFPGA，实现路由转发的工程。在此工程中，可以修改路由表，实现多功能的路由功能。-Based NetFPGA, forwarding the project to achieve routing. In this project, can modify the routing table, routing capabilities to achieve multi-functional.
comparer
- VHDL比较器，可直接使用QuatusII的project文件打开-VHDL comparator can be used directly QuatusII the project file open
ddrsdram_verilog
- 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with veri
EP1C3_12_5_RSV
- 基于ＦＰＧＡ的数字存储示波器，用ＶＨＤＬ实现的，压缩包里是Quartus工程。AD采样送进FPGA，存入SRAM后用DA在普通示波器上可以显示。-FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display.
aes_verilog
- A RTL verilog coding for the project AES, which is a cryptography based concepts
DDS_trans_final
- DDS芯片AD9854的配置文件，能配置正弦波的频率和幅度，也能配置相关的调制方式和调制参数，只要根据芯片资料给出合适的控制字入口参数即可，都是我在项目开发实际应用的代码，希望对大家有点帮助-AD9854 DDS chip, the configuration file, to configure the frequency and amplitude sine wave can also configure the relevant parameters of modulation and m
debounce_2_Verilog
- 用VerilogHDL编写的按键消抖程序 分频产生100Hz的按键采样时钟,采样时钟周期为10ms, 按键按下后,产生时间为10ms的低电平信号,即LED亮10m-*Project Name :debounce *Module Name :debounce *Target Device :Any Altera FPGA/CPLD Device *Clkin : 50MHz *Desisgner : zhaibin *Date : 2011-11-
arccos
- 一个求反余弦的cordic算法，整个工程。包括仿真。可以直接打开。-An inverse cosine of the cordic seeking algorithms, the whole project. Including the simulation. Can be directly opened.
verilog
- 一个可以综合的Verilog 7段秒表实例。上海交大微电子学院课程作业。-An example Verilog project. 7-segment
Altera-FPGACPLD
- Altera FPGACPLD设计(基础篇)配套光盘,提供了书中所有示例的完整工程文件、设计源文件和说明文件。 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Altera FPGACPLD Design (fundamental) supporting CD-ROM, the book provides a complete project files for al
DE0_D5M
- 这是在DE0板上实现的用D5M+VGA的图像实时显示程序，完整工程-This is achieved in DE0 board D5M+ VGA images with real-time display program, complete project
crc
- 自己写的循环冗余校验，进行了仿真，整个工程都在！-Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
Project
- 基于SOPC实现的俄罗斯方块,用VGA来做显示，PS2键盘来控制-SOPC-based implementation of Tetris, to do with the VGA display, PS2 keyboard to control the
Dice_game
- VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.